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71. 发明授权

US06979613B1 Method for fabricating a trench capacitor of DRAM 有权
标题翻译： DRAM的沟槽电容器的制造方法
公开(公告)号：US06979613B1
公开(公告)日：2005-12-27
申请号：US10707027
申请日：2003-11-16
申请人： Kuo-Chien Wu , Ping Hsu
发明人： Kuo-Chien Wu , Ping Hsu
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.
摘要翻译：一种制造深沟槽电容器的方法。提供了具有堆叠在其主表面上的衬垫氧化物层和衬垫氮化物层的衬底。通过衬垫氧化物层和衬垫氮化物层将深沟槽蚀刻到衬底中。节点电介质涂覆在深沟槽的内表面上。硅间隔层形成在节点电介质上的深沟槽的侧壁上。硅间隔层的上部掺杂有诸如BF 2 N的掺杂剂。选择性地去除硅间隔层的未掺杂部分以暴露节点电介质的一部分。将暴露的节点电介质剥离以露出衬底。由掺杂硅间隔层覆盖的剩余节点电介质形成保护间隔物，用于在随后的蚀刻工艺期间保护衬垫氧化物层不受腐蚀。

72. 发明授权

US06977715B2 Method for optimizing NILS of exposed lines 有权
标题翻译：优化裸露线的NILS的方法
公开(公告)号：US06977715B2
公开(公告)日：2005-12-20
申请号：US10709651
申请日：2004-05-19
申请人： Yuan-Hsun Wu
发明人： Yuan-Hsun Wu
IPC分类号： G03B27/32 , G03B27/42 , G03F1/14
CPC分类号： G03F1/36
摘要： A method for optimizing NILS of exposed lines includes providing a photomask layout which has a first straight line and a second straight line parallel with the first straight line and is applied to a Quasar 90 illumination, and adding a first assist pattern between the first and second straight lines, wherein the first assist pattern has a plurality of geometric patterns with similar size arranging as a line parallel with the first straight line.
摘要翻译：一种用于优化曝光线的NILS的方法包括提供光掩模布局，其具有与第一直线平行的第一直线和第二直线，并被应用于星形90照明，并且在第一与第二直线之间增加第一辅助图案直线，其中第一辅助图案具有排列成与第一直线平行的直线相同尺寸的多个几何图案。

73. 发明授权

US06905897B1 Wafer acceptance testing method and structure of a test key used in the method 有权
标题翻译：晶圆验收测试方法和方法中使用的测试键的结构
公开(公告)号：US06905897B1
公开(公告)日：2005-06-14
申请号：US10707398
申请日：2003-12-10
申请人： Ping Hsu
发明人： Ping Hsu
IPC分类号： G01R31/28 , H01L21/66 , H01L23/544 , H01L23/58 , H01L29/06 , H01L31/0328
CPC分类号： H01L22/34 , G01R31/2884
摘要： A wafer acceptance testing method for monitoring GC-DT misalignment and a test key structure are disclosed. The test key includes a deep trench capacitor structure biased to a first voltage (VDT). The deep trench capacitor structure includes a buried strap out diffusion region A GC-T electrode layout, which is biased to a second voltage (VGC-T), includes a plurality of columns of GC-T fingers. A GC-B electrode layout, which is biased to a third voltage (VGC-B), includes a plurality of columns of GC-B fingers that interdigitate the GC-T fingers. A first capacitance C1 of a first capacitor contributed by the GC-T fingers and the buried strap out diffusion region is measured. A second capacitance C2 of a second capacitor contributed by the GC-B fingers and the buried strap out diffusion region is measured. The first capacitance C1 and second capacitance C2 are compared, wherein when C1≠C2, GC-DT is misaligned.
摘要翻译：公开了用于监测GC-DT不对准的晶片验收测试方法和测试键结构。测试键包括偏置到第一电压（V SUB DT）的深沟槽电容器结构。深沟槽电容器结构包括被偏置到第二电压（V GC-T））的掩埋带出扩散区A GC-T电极布局，包括多列GC-T指。被偏置到第三电压（V GC-B））的GC-B电极布局包括多个GC-B指针列，其指示GC-T指状物。测量由GC-T指状物和掩埋带出扩散区域贡献的第一电容器的第一电容C 1 1。测量由GC-B手指和掩埋带出扩散区域贡献的第二电容器的第二电容C 2 2。比较第一电容C 1和第二电容C 2 2，其中当C 1> C 2 时， GC-DT未对齐。

74. 发明申请

US20030211688A1 METHOD OF FORMING POLY TIP OF FLOATING GATE IN SPLIT-GATE MEMORY 有权
标题翻译：在闸门存储器中形成浮动门的聚合方法
公开(公告)号：US20030211688A1
公开(公告)日：2003-11-13
申请号：US10292624
申请日：2002-11-13
申请人： NANYA TECHNOLOGY CORP
发明人： Yung-Meng Huang , Chi-Hei Lin , Ching-Nan Hsiao
IPC分类号： H01L029/788 , H01L021/336
CPC分类号： H01L29/42324 , H01L21/28273
摘要： The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.
摘要翻译：本发明提供了一种用于形成具有多个尖端的浮动栅极的方法。该方法包括为半导体衬底提供形成在半导体衬底上的栅介质层的步骤。然后在栅极电介质层上形成第一多晶硅层。在第一多晶硅层上形成硬掩模层。然后，在硬掩模层中形成开口以露出第一多晶硅层的一部分。接下来，在开口中形成多个间隔物。然后，去除硬掩模层和其下的第一多晶硅层以形成浮栅。

75. 发明授权

US09412433B2 Counter based design for temperature controlled refresh 有权
标题翻译：基于计数器的温度控制刷新设计
公开(公告)号：US09412433B2
公开(公告)日：2016-08-09
申请号：US14161655
申请日：2014-01-22
申请人： NANYA TECHNOLOGY CORP.
发明人： Donald Martin Morgan
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G11C11/40611
摘要： A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for receiving external commands to perform a refresh operation, and incrementing a count upon each received external command, wherein the refresh operation will be selectively skipped according to a value of the binary counter. The binary counter is activated to a first mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a first threshold and activated to a second mode when the temperature sensor determines the temperature operating condition of the DRAM goes below a second threshold lower than the first threshold.
摘要翻译： DRAM包括：用于监视DRAM的温度操作状态的温度传感器; 以及耦合到所述温度传感器的二进制计数器，用于接收执行刷新操作的外部命令，以及在每个所接收的外部命令时递增计数，其中根据二进制计数器的值选择性地跳过刷新操作。当温度传感器确定DRAM的温度操作条件低于第一阈值时，二进制计数器被激活到第一模式，并且当温度传感器确定DRAM的温度操作条件低于第二阈值时激活到第二模式比第一个门槛。

76. 发明授权

US09091929B2 Method of forming tight-pitched pattern 有权
标题翻译：形成紧密花纹图案的方法
公开(公告)号：US09091929B2
公开(公告)日：2015-07-28
申请号：US14249371
申请日：2014-04-10
申请人： NANYA TECHNOLOGY CORP.
发明人： Chun-Wei Wu
IPC分类号： G03F7/20 , G03F1/50
CPC分类号： G03F7/2022 , G03F1/50 , G03F7/203 , G03F7/70458 , G03F7/70466
摘要： A method of forming a tight-pitched pattern. A target pattern including a plurality of first stripe patterns is provided. Each of the first stripe patterns has a first width and a first length. A photomask includes a plurality of second stripe patterns corresponding to the first stripe patterns is provided. Each of the second stripe patterns has a second width and a second length. A first exposure process with the photomask is provided in an exposure system. The first exposure process uses a first light source with a higher resolution that is capable of resolving the second width of each of the second stripe patterns. Finally, a second exposure process with the photo-mask is provided in the exposure system. The second exposure process uses a second light source with a lower resolution that is not adequate to resolve the second width of each of the second stripe patterns.
摘要翻译：形成紧斜图案的方法。提供包括多个第一条纹图案的目标图案。每个第一条纹图案具有第一宽度和第一长度。光掩模包括与第一条纹图案相对应的多个第二条纹。每个第二条纹图案具有第二宽度和第二长度。在曝光系统中提供了具有光掩模的第一曝光过程。第一曝光过程使用具有更高分辨率的第一光源，其能够分辨每个第二条纹图案的第二宽度。最后，在曝光系统中提供具有光掩模的第二曝光处理。第二曝光过程使用具有较低分辨率的第二光源，其不足以解决每个第二条纹图案的第二宽度。

77. 发明授权

US09070584B2 Buried digitline (BDL) access device and memory array 有权
标题翻译：埋地数字线（BDL）接入设备和存储器阵列
公开(公告)号：US09070584B2
公开(公告)日：2015-06-30
申请号：US13901592
申请日：2013-05-24
申请人： NANYA TECHNOLOGY CORP.
发明人： Shyam Surthi , Lars Heineck
IPC分类号： H01L27/108 , H01L23/522
CPC分类号： H01L27/10894 , H01L23/5225 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.
摘要翻译：存储器阵列包括沿着第一方向延伸的多个数字线（DL）沟槽; DL沟槽之间的埋置数字线; 密封每个DL沟槽中的气隙的沟槽填充材料层; 沿着第二方向延伸的多个字线（WL）沟槽; 设置在埋地数字线一端的有源斩波（AC）沟槽; 气隙中的屏蔽层; 以及围绕AC沟槽的侧壁的侧壁导体。

78. 发明授权

US09041154B2 Contact structure and semiconductor memory device using the same 有权
标题翻译：接触结构和使用其的半导体存储器件
公开(公告)号：US09041154B2
公开(公告)日：2015-05-26
申请号：US13786463
申请日：2013-03-06
申请人： NANYA TECHNOLOGY CORP.
发明人： Chien-An Yu , Chih-Huang Wu
IPC分类号： H01L29/00 , H01L27/04 , H01L23/522 , H01L27/06 , H01L27/108 , H01L49/02
CPC分类号： H01L27/04 , H01L23/5223 , H01L27/0629 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L28/40 , H01L28/60 , H01L28/91 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
摘要翻译：半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。在存储器阵列区域中至少提供一个电容器结构。电容器结构包括嵌入在第二电介质层中的电极材料层。半导体存储器件还包括包括电极材料层的接触结构。

79. 发明授权

US09041099B2 Single-sided access device and fabrication method thereof 有权
标题翻译：单面接入装置及其制造方法
公开(公告)号：US09041099B2
公开(公告)日：2015-05-26
申请号：US13084533
申请日：2011-04-11
申请人： Shyam Surthi , Sheng-Wei Yang
发明人： Shyam Surthi , Sheng-Wei Yang
IPC分类号： H01L29/66 , H01L27/108 , H01L29/78 , H01L29/423 , H01L29/10
CPC分类号： H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/1037 , H01L29/4236 , H01L29/42372 , H01L29/66795 , H01L29/785
摘要： The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer.
摘要翻译：本发明提供了一种包括源极区和漏极区的有源鳍结构的单面存取装置。介于所述源极区域和所述漏极区域之间的绝缘层; 设置在所述活动鳍结构的一侧的沟槽隔离结构; 设置在与沟槽隔离结构相对的有源鳍结构的另一侧的单面侧壁栅电极，使得活性鳍结构被沟槽隔离结构和单侧壁栅电极夹在中间; 以及从所述单面侧壁栅电极侧向和电气地延伸并且嵌入在所述绝缘层下方的所述源极区域和所述漏极区域之间的栅极突起。

80. 发明申请

US20150067197A1 DATA PATTERN GENERATION FOR I/O TRAINING AND CHARACTERIZATION 有权
标题翻译：用于I / O培训和表征的数据模式生成
公开(公告)号：US20150067197A1
公开(公告)日：2015-03-05
申请号：US14017277
申请日：2013-09-03
申请人： NANYA TECHNOLOGY CORP.
发明人： Timothy M. Hollis , Jeffrey P. Wright , Kang-Yong Kim , Eric J. Stave
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F3/061 , G06F3/0653 , G06F3/0683 , G06F12/00 , G11C11/40 , G11C29/022 , G11C29/50012
摘要： A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path.
摘要翻译：可以在不访问主存储器阵列的情况下执行输出数据路径的表征的存储器结构包括：多个输出数据路径; 耦合到输出数据路径的多个寄存器。寄存器包括：至少第一模式寄存器和第二模式寄存器，用于分别存储第一数据模式和第二数据模式; 以及至少第一映射寄存器，用于存储多个二进制值，其中每个二进制值指示第一数据模式或第二数据模式是否应映射到相应的输出数据路径。

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