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61. 发明授权

US09543968B2 Output control circuit for semiconductor apparatus and output driving circuit including the same 有权
标题翻译：用于半导体装置的输出控制电路和包括其的输出驱动电路
公开(公告)号：US09543968B2
公开(公告)日：2017-01-10
申请号：US15059453
申请日：2016-03-03
申请人： SK hynix Inc.
发明人： Jong Ho Jung , Da In Im
IPC分类号： G11C7/00 , H03L7/081 , H03K5/14 , H03L7/08 , H03L7/00 , H03K17/22 , H03K5/00
CPC分类号： H03L7/0812 , H03K5/14 , H03K17/22 , H03K2005/00097 , H03L7/00 , H03L7/08
摘要： An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.
摘要翻译：输出控制电路可以包括周期设置信号生成单元，其被配置为响应于延迟锁定环（DLL）锁定信号和输出使能复位信号而输出在指定时段期间使能的建立信号。输出控制电路还可以包括：时钟分割单元，被配置为响应于建立信号以预设的分频比来划分内部时钟，并输出分频时钟。此外，输出控制电路可以包括移位单元，其被配置为响应于划分的时钟将建立信号第一时间移位，并输出第一延迟设置信号。此外，输出控制电路可以包括：输出单元，被配置为响应于分频时钟接收和处理第一延迟设置信号，并输出输出使能复位信号。

62. 发明授权

US09531363B2 Methods and apparatuses including command latency control circuit 有权
标题翻译：方法和装置包括命令等待时间控制电路
公开(公告)号：US09531363B2
公开(公告)日：2016-12-27
申请号：US14698550
申请日：2015-04-28
申请人： Micron Technology, Inc.
发明人： Kazutaka Miyano
IPC分类号： H03L7/06 , H03K5/135 , H03K5/14 , H03K3/037 , H03L7/081
CPC分类号： H03K5/135 , G11C7/106 , G11C7/1066 , G11C2207/2272 , H03K3/037 , H03K5/14 , H03L7/0812
摘要： Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.
摘要翻译：描述包括等待时间控制电路的方法和装置。一种示例性装置包括：延迟线电路，被配置为延迟时钟信号;锁存器控制电路，被配置为接收时钟信号和延迟的时钟信号。锁存器控制电路被配置为基于与第一时钟信号相关联的计数来提供第一控制信号。锁存控制电路还被配置为基于与第一时钟信号相关联的计数来提供第二控制信号。第二时钟信号相对于第一时钟信号被延迟大致等于时钟信号和延迟的时钟信号之间的延迟的量。该示例设备还包括锁存电路，其被配置为响应于第一控制信号锁存输入信号。锁存电路还被配置为响应于第二控制信号向锁存的信号提供锁存信号。

63. 发明申请

US20160363619A1 ON-CHIP APPARATUS AND METHOD FOR JITTER MEASUREMENT 有权
标题翻译：芯片测量装置及其测量方法
公开(公告)号：US20160363619A1
公开(公告)日：2016-12-15
申请号：US14949888
申请日：2015-11-24
申请人： Faraday Technology Corp.
发明人： Pei-Yuan Chou , Jinn-Shyan Wang , Yeong-Jar Chang
IPC分类号： G01R29/26 , G01R35/00 , H03K5/14
CPC分类号： H03K5/14 , G01R31/31709 , G01R31/31937 , H03K2005/00019
摘要： An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.
摘要翻译：用于抖动测量的装置包括第一延迟电路，第二延迟电路和控制电路。第一延迟电路对输入信号施加初步相位延迟以产生延迟的输入信号。第二延迟电路与第一延迟电路一起工作，以对延迟的输入信号施加精细相位延迟。控制电路控制由第一和第二延迟电路施加的延迟量，并且根据由第一和第二延迟电路的延迟元件分别施加的延迟量微调延迟输入信号的相位延迟，并且估计或计算根据第一和第二延迟电路的调整结果，输入信号的抖动窗口。

64. 发明申请

US20160241224A1 DIGITAL DELAY UNIT AND SIGNAL DELAY CIRCUIT 有权
标题翻译：数字延迟单元和信号延迟电路
公开(公告)号：US20160241224A1
公开(公告)日：2016-08-18
申请号：US15008919
申请日：2016-01-28
申请人： Silicon Motion, Inc.
发明人： Yu-Hsuan CHENG
IPC分类号： H03K5/14
CPC分类号： H03K5/14 , H03K2005/00019 , H03K2005/00234
摘要： An example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.
摘要翻译：本发明的实例提供了由多个NAND门构成的数字延迟单元。数字延迟单元包括第一延迟路径和第二延迟路径。第一延迟路径耦合在第一输入端和输出端之间，以提供由一个与非门引起的基本时间延迟。第二延迟路径耦合在第二输入端和输出端之间以提供至少三个基本时间延迟。

65. 发明申请

US20160209859A1 APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES 有权
公开(公告)号：US20160209859A1
公开(公告)日：2016-07-21
申请号：US15086763
申请日：2016-03-31
申请人： Micron Technology, Inc.
发明人： Trismardawi Tanadi
IPC分类号： G05F1/66 , H03K17/22 , H03K5/14 , H01L25/065
CPC分类号： G05F1/66 , G06F1/26 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L2924/0002 , H03K5/14 , H03K17/223 , H03K2005/00234 , H01L2924/00
摘要： An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

66. 发明申请

US20160182028A1 DELAY CIRCUIT 有权
标题翻译：延时电路
公开(公告)号：US20160182028A1
公开(公告)日：2016-06-23
申请号：US14718857
申请日：2015-05-21
申请人： SK hynix Inc.
发明人： Inhwa JUNG
IPC分类号： H03K5/14
CPC分类号： H03K5/14 , H03K2005/00065
摘要： A delay circuit may include a delay path including a fine delay line and a coarse delay line a replica delay path including a replica fine delay line and a replica coarse delay line, and a tuning unit that compares a phase of a first signal obtained by delaying an input signal through the delay path with a phase of a second signal obtained by delaying the input signal through the replica delay path, and generates a tuning code in a tuning mode.
摘要翻译：延迟电路可以包括包括精细延迟线和粗略延迟线的延迟路径，复制延迟路径包括复制精细延迟线和复制粗略延迟线，以及调谐单元，其比较通过延迟获得的第一信号的相位通过延迟路径的输入信号，通过将输入信号延迟通过复制延迟路径而获得的具有第二信号的相位，并且在调谐模式中生成调谐码。

67. 发明授权

US09325330B2 Semiconductor device including a clock adjustment circuit 有权
标题翻译：半导体装置包括时钟调整电路
公开(公告)号：US09325330B2
公开(公告)日：2016-04-26
申请号：US14509894
申请日：2014-10-08
申请人： MICRON TECHNOLOGY, INC.
发明人： Nobutaka Taniguchi
IPC分类号： H03L7/00 , H03L7/085 , H03K5/14
CPC分类号： H03L7/085 , H03K5/14 , H03L7/0812
摘要： Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.
摘要翻译：本文公开了一种半导体器件，其包括第一电路，该第一电路包括响应于第一和第二时钟信号和控制信号而被级联并配置的多个第一逻辑元件，以产生指示第一逻辑的第一数量的控制信息在由第一时钟信号的逻辑电平的第一变化和第二时钟信号的逻辑电平的第二变化所限定的时段期间，控制信号通过其传播的元件，第一和第二变化彼此相邻地发生以及包括延迟电路的第二电路，该延迟电路经配置以接收第一时钟信号和控制信息，并且通过响应于控制信息的量延迟第一时钟信号产生第三时钟信号。

68. 发明申请

US20160111061A1 LOW POWER HIGH FREQUENCY DIGITAL PULSE FREQUENCY MODULATOR 有权
标题翻译：低功率高频数字脉冲频率调制器
公开(公告)号：US20160111061A1
公开(公告)日：2016-04-21
申请号：US14129269
申请日：2013-06-10
申请人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
发明人： Fenardi THENUS , Peng ZOU , Raghu Nandan CHEPURI , Henry K. KOERTZEN
IPC分类号： G09G5/00 , H03K17/284 , G06F3/041 , H03K7/06 , H02M3/158 , H03K5/14 , H03K7/08
CPC分类号： G09G5/006 , G06F3/0412 , G09G2330/021 , H02M3/158 , H02M3/1584 , H02M2001/0009 , H02M2001/0032 , H02M2003/1586 , H03K5/14 , H03K7/06 , H03K7/08 , H03K17/284 , Y02B70/16
摘要： Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.
摘要翻译：描述了一种装置，包括：可编程延迟线（PDL），用于接收作为输入的脉宽调制（PWM）信号并产生第一输出; 选择单元，其可操作以提供PWM信号或其反相版本作为第二输出; 以及连接到PDL的顺序单元，该顺序单元用第一输出对第二输出进行采样，该顺序单元用于产生脉冲 - 频率调制（PFM）输出。还描述了一种电压调节器，其包括：用于耦合到负载的相互耦合的片上电感器; 耦合到相互耦合的片上电感器的桥，包括低侧开关和高侧开关; PWM控制器，用于在第一负载电流期间控制所述低侧和高侧开关; 以及PFM控制器，用于在第二负载电流期间控制低侧和高侧开关，所述第二负载电流小于所述第一负载电流，所述PFM控制器包括：比较器，用于将所述负载的输出电压与参考电压; 以及耦合到比较器的用于确定高侧开关的导通持续时间的第一PDL。

69. 发明授权

US09281811B2 Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency 有权
标题翻译：电路，方法和合成器，用于产生具有可选频率的合成信号
公开(公告)号：US09281811B2
公开(公告)日：2016-03-08
申请号：US14546127
申请日：2014-11-18
申请人： Intel IP Corporation
发明人： Michael Bruennert , Andreas Menkhoff
IPC分类号： H03K5/14
CPC分类号： H03K5/14
摘要： A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.
摘要翻译：用于产生具有可选频率的振荡的电路包括延迟发生器，其被配置为识别第一时刻，所述第一时刻相对于以预定时钟频率振荡的时钟信号的信号边缘被延迟。延迟元件被配置为提供信号边缘，信号边缘相对于第一时刻被延迟，使得在对应于合成信号的信号边缘的第二时刻提供信号边缘。

70. 发明申请

US20160065194A1 DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT 有权
标题翻译：具有可变延迟线单元的延迟线电路
公开(公告)号：US20160065194A1
公开(公告)日：2016-03-03
申请号：US14939255
申请日：2015-11-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tsung-Ching HUANG , Chih-Chang LIN , Fu-Lung HSUEH
IPC分类号： H03K5/14
CPC分类号： H03K5/14 , H03K5/133 , H03K2005/00019 , H03K2005/00071
摘要： A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.
摘要翻译：延迟线电路包括多个延迟电路和可变延迟线电路。多个延迟电路接收输入信号并产生第一输出信号。第一输出信号对应于延迟输入信号或反相输入信号。可变延迟线电路接收第一输出信号。可变延迟线电路包括输入端，输出端，第一和第二路径。输入端被配置为接收第一输出信号。输出端被配置为输出第二输出信号。第一路径包括第一多个逆变器和第一电路。第二路径包括第二多个反相器和第二电路。基于从延迟线控制器接收的控制信号，接收到的第一输出信号通过第一或第二路径选择性地发送。

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