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61. 发明授权

US08042261B2 Method for fabricating embedded thin film resistors of printed circuit board 有权
标题翻译：制造印刷电路板的嵌入薄膜电阻的方法
公开(公告)号：US08042261B2
公开(公告)日：2011-10-25
申请号：US12356083
申请日：2009-01-20
申请人： Sung-Ling Su
发明人： Sung-Ling Su
IPC分类号： H01C17/06
CPC分类号： H05K1/167 , C25D5/022 , C25D7/12 , H05K3/062 , H05K3/064 , H05K3/184 , H05K2201/0969 , H05K2203/1453 , Y10T29/49082 , Y10T29/49099 , Y10T29/49124 , Y10T29/49151
摘要： A method for fabricating the embedded thin film resistors of a printed circuit board is provided. The embedded thin film resistors are formed using a resistor layer built in the printed circuit board. In comparison with conventional discrete resistors, embedded thin film resistors contribute to a smaller printed circuit board as the space for installing conventional resistors is saved, and better signal transmission speed and quality as the parasitic capacitive reactance effect caused by two contact ends of the conventional resistors is also avoided. The method for fabricating the embedded thin film resistors provided by the invention can be conducted using the process and equipment for conventional printed circuit boards and thereby saving the investment on new types of equipment. The method can be applied in the mass production of printed circuit boards and thereby reduce the manufacturing cost significantly.
摘要翻译：提供一种制造印刷电路板的嵌入式薄膜电阻器的方法。嵌入式薄膜电阻器使用内置在印刷电路板中的电阻层形成。与传统的分立电阻器相比，嵌入式薄膜电阻器有助于更小的印刷电路板，因为节省了安装常规电阻器的空间，并且由于传统电阻器的两个接触端引起的寄生电容电抗效应，信号传输速度和质量更好也避免了。本发明提供的嵌入式薄膜电阻器的制造方法可以使用常规印刷电路板的工艺和设备进行，从而节省对新型设备的投资。该方法可以用于批量生产印刷电路板，从而显着降低制造成本。

62. 发明授权

US08039755B2 Method for manufacturing a printed circuit board element as well as a printed circuit board element 有权
标题翻译：印刷电路板元件的制造方法以及印刷电路板元件
公开(公告)号：US08039755B2
公开(公告)日：2011-10-18
申请号：US12465901
申请日：2009-05-14
申请人： Wolfgang Bauer , Johannes Stahr
发明人： Wolfgang Bauer , Johannes Stahr
IPC分类号： H05K1/03
CPC分类号： H05K1/167 , H05K1/095 , H05K3/244 , H05K3/28 , H05K3/382 , H05K3/383 , H05K3/384 , H05K2203/1453 , Y10T29/49082 , Y10T29/49083 , Y10T29/49085 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A circuit board element and production thereof are disclosed, whereby a noble metal is applied to a structured conductor layer on a circuit board substrate, comprising said conductor layer. The conductor layer is roughened on the surface, preferably after the structuring thereof and the noble metal applied as a layer, essentially on all of the structured roughened conductor layer, whereupon the noble metal layer surface is given a corresponding roughness.
摘要翻译：公开了一种电路板元件及其制造方法，由此将贵金属应用于包括所述导体层的电路板基板上的结构化导体层。导体层在表面上粗糙化，优选在其构造之后，并且作为层施加的贵金属基本上在所有结构化的粗糙导体层上，由此赋予贵金属层表面相应的粗糙度。

63. 发明申请

US20110236593A1 Treatment Method Using Plasma 审中-公开
标题翻译：使用等离子体的处理方法
公开(公告)号：US20110236593A1
公开(公告)日：2011-09-29
申请号：US13122385
申请日：2009-10-05
申请人： Akitoshi Okino , Hidekazu Miyahara
发明人： Akitoshi Okino , Hidekazu Miyahara
IPC分类号： B05D3/10 , B05D5/00 , B05D5/12 , B05D1/02 , B05D1/00
CPC分类号： H05K3/105 , C23C18/00 , C23C18/06 , C23C18/1216 , C23C18/14 , H01L27/1292 , H05K1/16 , H05K1/167 , H05K2203/095
摘要： The invention is related to a treatment for a base material using plasma. Various particulate substances, porous substances, or film-state substances can be easily formed on the base material. Alternatively, a particulate substance, a porous substance, or a film-state substance, such as ceramic, can be formed even on a base material having low heat resistance. In a treatment method using plasma, in which the plasma is irradiated on a precursor substance 12 deposited on a surface of a base material 10 and a portion of the component materials of the precursor substance 12 is removed, the base material 10 is in particulate form, filamentous form, or three-dimensional form. The precursor substance 12 is liquid, gas, suspension, powder, or a solid applied to the base material. The precursor substance 12 is deposited on the base material 10 by coating, spraying, transfer, or printing.
摘要翻译：本发明涉及使用等离子体的基材的处理。在基材上可以容易地形成各种颗粒物质，多孔物质或膜状物质。或者，即使在具有低耐热性的基材上也可以形成颗粒物质，多孔物质或诸如陶瓷的膜状物质。在使用等离子体的处理方法中，其中等离子体照射在沉积在基材10的表面上的前体物质12和前体物质12的一部分成分材料上，基材10为颗粒形式，丝状或三维形式。前体物质12是施加到基材的液体，气体，悬浮液，粉末或固体。前体物质12通过涂覆，喷涂，转印或印刷沉积在基材10上。

64. 发明授权

US07986037B2 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US07986037B2
公开(公告)日：2011-07-26
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/52
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

65. 发明申请

US20110168564A1 PLATING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD AND CIRCUIT BOARD FABRICATION METHOD 有权
标题翻译：电镀方法，半导体器件制造方法和电路板制造方法
公开(公告)号：US20110168564A1
公开(公告)日：2011-07-14
申请号：US13043854
申请日：2011-03-09
申请人： Masataka Mizukoshi , Kanae Nakagawa , Takeshi Shioga , Kazuaki Kurihara , John David Baniecki
发明人： Masataka Mizukoshi , Kanae Nakagawa , Takeshi Shioga , Kazuaki Kurihara , John David Baniecki
IPC分类号： C25D7/12
CPC分类号： H01L24/91 , H01L21/4846 , H01L21/4857 , H01L21/486 , H01L21/76801 , H01L21/7687 , H01L21/76873 , H01L21/76874 , H01L21/76885 , H01L23/5283 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L24/45 , H01L24/48 , H01L24/82 , H01L2224/02333 , H01L2224/0401 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05655 , H01L2224/1134 , H01L2224/12105 , H01L2224/13144 , H01L2224/13147 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48132 , H01L2224/73267 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01056 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/381 , H05K3/4602 , H05K3/4661 , H05K2201/0209 , H05K2201/086 , H05K2201/09509 , H05K2203/0195 , H05K2203/0228 , H01L2224/13099 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
摘要翻译：电镀方法包括在基板16上形成树脂层10的步骤; 用切割工具12切割树脂层10的表面部分的步骤; 通过无电解电镀在树脂层10上形成种子层36的步骤; 以及通过电镀在种子层36上形成电镀膜44的步骤。可以赋予树脂层10的表面适当的粗糙度，由此能够充分确保种子层36与树脂层10之间的粘附性。在树脂层10的表面没有形成过度的深孔，如通过去污处理，从而可以在树脂层10上形成光致抗蚀剂膜40的微粉化图案。因此，可以在确保了高可靠性的窄间距树脂层10。

66. 发明授权

US07948355B2 Embedded resistor devices 失效
标题翻译：嵌入式电阻器件
公开(公告)号：US07948355B2
公开(公告)日：2011-05-24
申请号：US11852244
申请日：2007-09-07
申请人： Chang-Lin Wei , Chang-Sheng Chen , Cheng-Hua Tsai , Syun Yu , Chin-Sun Shyu
发明人： Chang-Lin Wei , Chang-Sheng Chen , Cheng-Hua Tsai , Syun Yu , Chin-Sun Shyu
IPC分类号： H01C1/012
CPC分类号： H05K1/167 , H05K1/0237 , H05K1/0298 , H05K2201/09781
摘要： An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.
摘要翻译：嵌入式电阻器件包括电阻器，接地平面位于电阻器的第一侧附近并电耦合到电阻器的第一端，在接地平面处设有一个孔，第一电介质层位于电阻器和地之间平面，电耦合到电阻器的不同于电阻器的第一端并部分地围绕电阻器的第二端的导线被用作支持电阻器的电阻器涂覆工艺的辅助件，并且提供在导电线处的嵌入式电阻器件的端子，位于接地平面的与电阻器的第一侧不同的第二侧附近的导电区域，在接地平面和导电区域之间存在第二介电层，并且导电路径以通过该孔将导线电连接到导电区域。

67. 发明申请

US20110061902A1 Circuit board and method of manufacturing the same 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：US20110061902A1
公开(公告)日：2011-03-17
申请号：US12654674
申请日：2009-12-29
申请人： Hee Bum Lee , Kyoung Soo Chae
发明人： Hee Bum Lee , Kyoung Soo Chae
IPC分类号： H05K1/00
CPC分类号： H05K1/167 , H05K1/0206 , H05K1/0209 , H05K3/4629 , H05K3/4644 , H05K3/4685 , H05K2201/09245 , H05K2201/09781
摘要： There is provided a circuit board. The circuit board according to an aspect of the invention may include: an insulating base body; a plurality of circuit patterns including a first conductive pattern and a second conductive pattern facing the first conductive pattern at a predetermined interval therebetween; a printed resistor connecting the first conductive pattern and the second conductive pattern; and a heat radiation pattern provided on the insulating base body and overlapping at least partially overlapping the printed resistor.According to an aspect of the invention, a circuit board facilitating a design of a heating structure by forming a printed resistor on a circuit board and forming a heat radiation structure overlapping or connected to the printed resistor, and a method of manufacturing the same can be provided.
摘要翻译：提供了一个电路板。根据本发明的一个方面的电路板可以包括：绝缘基体; 多个电路图形，包括第一导电图案和第二导电图案，其间以预定的间隔面对第一导电图案; 连接第一导电图案和第二导电图案的印刷电阻器; 以及设置在所述绝缘基体上并与所述印刷电阻器至少部分重叠的重叠的热辐射图案。根据本发明的一个方面，通过在电路板上形成印刷电阻器并形成与印刷电阻器重叠或连接的散热结构的便于设计加热结构的电路板及其制造方法可以是提供。

68. 发明申请

US20110058291A1 GEOMETRIC CONFIGURATION OR ALIGNMENT OF PROTECTIVE MATERIAL IN A GAP STRUCTURE FOR ELECTRICAL DEVICES 有权
标题翻译：电气设备间隙结构中保护材料的几何配置或对准
公开(公告)号：US20110058291A1
公开(公告)日：2011-03-10
申请号：US12878344
申请日：2010-09-09
申请人： Lex Kosowsky , Robert Fleming
发明人： Lex Kosowsky , Robert Fleming
IPC分类号： H02H9/00 , H01C7/10 , H01C7/12 , H05K1/00 , H05K7/00 , H02H3/22 , H03H11/40
CPC分类号： H01C7/10 , H01C7/12 , H05K1/0257 , H05K1/0259 , H05K1/167 , H05K2201/0738
摘要： an electrical device that includes a first electrode and a second electrode that are separated from one another so as to form a gap structure. A layer of protective material spans the gap structure to contact the first electrode and the second electrode. A dimension of the gap structure, corresponding to a separation distance between the first electrode and the second electrode, is varied and includes a minimum separation distance that coincides with a critical path of the layer of protective material between the first electrode and the second electrode.
摘要翻译：电气装置，其包括彼此分离以形成间隙结构的第一电极和第二电极。一层保护材料跨越间隙结构以接触第一电极和第二电极。相应于第一电极和第二电极之间的间隔距离的间隙结构的尺寸是变化的并且包括与第一电极和第二电极之间的保护材料层的关键路径一致的最小间隔距离。

69. 发明授权

US07883643B2 Overvoltage protection materials and process for preparing same 失效
标题翻译：过电压保护材料及其制备方法
公开(公告)号：US07883643B2
公开(公告)日：2011-02-08
申请号：US10274904
申请日：2002-10-21
申请人： Chi-Ming Chan , Kai-Mo Ng , Catherine Yuen-Chien Wong , Ying Kit Cheung
发明人： Chi-Ming Chan , Kai-Mo Ng , Catherine Yuen-Chien Wong , Ying Kit Cheung
IPC分类号： H01C7/12 , H01C7/10
CPC分类号： H01B1/22 , H05K1/0257 , H05K1/0259 , H05K1/167 , H05K2201/0738 , Y10T428/257 , Y10T428/31663
摘要： The invention provides a process for preparing an overvoltage protection material comprising: (i) preparing a mixture comprising a polymer binder precursor and a conductive material; and (ii) heating the mixture to cause reaction of the polymer binder precursor and generate a polymer matrix having conductive material dispersed therein, wherein the polymer binder precursor is chosen such that substantially no solvent is generated during the reaction.
摘要翻译：本发明提供一种制备过电压保护材料的方法，包括：（i）制备包含聚合物粘合剂前体和导电材料的混合物; 和（ii）加热混合物以引起聚合物粘合剂前体的反应并产生其中分散有导电材料的聚合物基质，其中选择聚合物粘合剂前体使得在反应期间基本上不产生溶剂。

70. 发明申请

US20100314233A1 HIGH-FREQUENCY SWITCH IN MULTI-LAYER SUBSTRATE 有权
标题翻译：多层基板中的高频开关
公开(公告)号：US20100314233A1
公开(公告)日：2010-12-16
申请号：US12860739
申请日：2010-08-20
申请人： CHANG-LIN WEI , CHING-LIANG WENG , UEI-MING JOW , YING-JIUNN LAI , SYUN YU , CHANG-SHENG CHEN
发明人： CHANG-LIN WEI , CHING-LIANG WENG , UEI-MING JOW , YING-JIUNN LAI , SYUN YU , CHANG-SHENG CHEN
IPC分类号： H03K17/975
CPC分类号： H05K1/162 , H01P1/15 , H05K1/0237 , H05K1/113 , H05K1/165 , H05K1/167 , H05K3/4644 , H05K2201/09672
摘要： A switch module consists of a build-up multi-layer structure and some passive devices. The build-up multi-layer structure has multitudes of conductive layers and dielectric layers laminated upon each another. At least one dielectric layer is interfered between any two conductive layers. Any one passive device is a portion of at least one conductive layer and electrically connects multitudes of conductive pads on the surface of the build-up multi-layer structure.
摘要翻译：交换机模块由建立的多层结构和一些无源设备组成。积层多层结构具有彼此层叠的多个导电层和电介质层。至少一个电介质层在任何两个导电层之间被干扰。任何一个无源器件是至少一个导电层的一部分，并且电连接多层结构的表面上的多个导电焊盘。

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