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61. 发明授权

US08230304B2 Wireless transmit/receive unit having a turbo decoder with circular redundancy code signature comparison and method 失效
标题翻译：具有循环冗余码签名比较和方法的turbo解码器的无线发射/接收单元
公开(公告)号：US08230304B2
公开(公告)日：2012-07-24
申请号：US12146856
申请日：2008-06-26
申请人： David S. Bass
发明人： David S. Bass
IPC分类号： H03M13/00
CPC分类号： H03M13/6588 , H03M13/09 , H03M13/2957 , H03M13/2975 , H04L1/00 , H04L1/0051 , H04L1/0066
摘要： An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.
摘要翻译：提供了一种用于无线通信系统的无线发射接收单元（WTRU）的迭代turbo解码器和用于对接收到的通信信号数据进行纠错的方法。解码器通过使用签名码来实现停止规则，以确定解码器数据的连续迭代是否相同。

62. 发明授权

US08136006B2 Turbo decoding apparatus and method 有权
标题翻译： Turbo解码装置及方法
公开(公告)号：US08136006B2
公开(公告)日：2012-03-13
申请号：US12262844
申请日：2008-10-31
申请人： Sook-Min Park
发明人： Sook-Min Park
IPC分类号： H03M13/00
CPC分类号： H03M13/2969 , H03M13/6502 , H03M13/6505 , H03M13/6577 , H03M13/6588
摘要： A turbo decoding method and apparatus for performing iterative decoding on a received signal is provided. A decoder receives a signal and an (N−1)th decoding result, performs Nth decoding thereon, and outputs first extrinsic information. A transformer reduces a bit width of the first extrinsic information output from the decoder and outputs second extrinsic information. A memory stores the second extrinsic information output from the transformer. A de-transformer de-transforms the second extrinsic information stored in the memory, to third extrinsic information having a same bit width as that of the first extrinsic information, and inputs the third extrinsic information to the decoder.
摘要翻译：提供了一种用于对接收信号执行迭代解码的turbo解码方法和装置。解码器接收信号和第（N-1）个解码结果，对其进行第N次解码，并输出第一外在信息。变压器减小从解码器输出的第一外部信号的位宽度，并输出第二外在信息。存储器存储从变压器输出的第二外部信号。去变压器将存储在存储器中的第二外部信号转换为与第一外在信息具有相同位宽的第三外在信息，并将第三外在信息输入到解码器。

63. 发明授权

US08074157B2 Methods and apparatus for reduced complexity soft-output viterbi detection 失效
标题翻译：降低复杂度软输出维特比检测的方法和装置
公开(公告)号：US08074157B2
公开(公告)日：2011-12-06
申请号：US12017547
申请日：2008-01-22
申请人： Erich F Haratsch
发明人： Erich F Haratsch
IPC分类号： H03M13/03
CPC分类号： H03M13/4107 , H03M13/6569 , H03M13/6577 , H03M13/6588
摘要： Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits. A sequence detector is provided that comprises a branch metrics unit for determining branch metrics having a first precision; a programmable precision conversion unit for converting the branch metrics having the first precision to branch metrics having a desired precision; and an add-compare select unit for computing path metrics based on the desired precision branch metrics. The Soft-Output Viterbi processor optionally processes a trellis having a reduced number of states relative to a trellis processed by the sequence detector.
摘要翻译：提供了降低复杂性的软输出维特比检测方法和装置。软输出维特比算法通过使用分支度量单位确定分支度量来处理信号; 使用第一加法比较选择单元确定用于序列检测的幸存路径; 以及确定用于使用第二加法比较选择单元生成一个或多个比特可靠性值的幸存路径，其中所述第一和第二加法比较选择单元处理由所述分支度量单元确定的分支度量。第一和第二加法比较选择单元可以可选地处理具有不同位数的分支度量。提供了一种序列检测器，其包括用于确定具有第一精度的分支度量的分支度量单元; 用于将具有第一精度的分支度量转换成具有期望精度的分支度量的可编程精度转换单元; 以及用于基于期望的精度分支度量来计算路径度量的加法比较选择单元。软输出维特比处理器可选地处理具有相对于由序列检测器处理的网格的状态数量减少的网格。

64. 发明申请

US20100067598A1 Method and System for LLR Buffer Reduction in a Wireless Communication Modem 有权
标题翻译：无线通信调制解调器中LLR缓冲区减少的方法和系统
公开(公告)号：US20100067598A1
公开(公告)日：2010-03-18
申请号：US12405649
申请日：2009-03-17
申请人： Hemanth Sampath , Avneesh Agrawal , Jeremy H. Lin
发明人： Hemanth Sampath , Avneesh Agrawal , Jeremy H. Lin
IPC分类号： H04L5/12 , H04L27/06
CPC分类号： H03M13/45 , H03M13/6588 , H04L1/0046 , H04L1/1819 , H04L1/1822 , H04L1/1835 , H04L1/1845 , H04L5/0007 , H04L25/067
摘要： A system involves a transmitting device (for example, a first wireless communication device) and a receiving device (for example, a second wireless communication device). In the receiving device, LLR (Log-Likelihood Ratio) values are stored into an LLR buffer. LLR bit width is adjusted as a function of packet size of an incoming transmission to reduce the LLR buffer size required and/or to prevent LLR buffer capacity from being exceeded. The receiver may use a higher performance demodulator in order to maintain performance despite smaller LLR bit width. In the transmitting device, encoder code rate is adjusted as a function of receiver LLR buffer capacity and packet size of the outgoing transmission such that receiver LLR buffer capacity is not exceeded. Any combination of receiver LLR bit width adjustment, demodulator selection, and encoder code rate adjustment can be practiced to reduce LLR buffer size required while maintaining performance.
摘要翻译：系统涉及发送设备（例如，第一无线通信设备）和接收设备（例如，第二无线通信设备）。在接收设备中，将LLR（对数似然比）值存储到LLR缓冲器中。根据输入传输的分组大小调整LLR比特宽度，以减少所需的LLR缓冲区大小和/或防止超出LLR缓冲区容量。接收机可以使用更高性能的解调器，以便尽管较小的LLR位宽度来保持性能。在发送设备中，根据接收机LLR缓冲器容量和输出传输的分组大小调节编码器码率，使得接收机LLR缓冲器容量不被超过。可以实现接收机LLR位宽度调整，解调器选择和编码器码率调整的任何组合，以在保持性能的同时减少所需的LLR缓冲区大小。

65. 发明申请

US20090217127A1 TURBO DECODING APPARATUS AND METHOD 有权
标题翻译：涡轮解码装置和方法
公开(公告)号：US20090217127A1
公开(公告)日：2009-08-27
申请号：US12262844
申请日：2008-10-31
申请人： Sook-Min PARK
发明人： Sook-Min PARK
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2969 , H03M13/6502 , H03M13/6505 , H03M13/6577 , H03M13/6588
摘要： A turbo decoding method and apparatus for performing iterative decoding on a received signal is provided. A decoder receives a signal and an (N−1)th decoding result, performs Nth decoding thereon, and outputs first extrinsic information. A transformer reduces a bit width of the first extrinsic information output from the decoder and outputs second extrinsic information. A memory stores the second extrinsic information output from the transformer. A de-transformer de-transforms the second extrinsic information stored in the memory, to third extrinsic information having a same bit width as that of the first extrinsic information, and inputs the third extrinsic information to the decoder.
摘要翻译：提供了一种用于对接收信号执行迭代解码的turbo解码方法和装置。解码器接收信号和第（N-1）个解码结果，对其进行第N次解码，并输出第一外在信息。变压器减小从解码器输出的第一外部信号的位宽度，并输出第二外在信息。存储器存储从变压器输出的第二外部信号。去变压器将存储在存储器中的第二外部信号转换为与第一外在信息具有相同位宽的第三外在信息，并将第三外在信息输入到解码器。

66. 发明申请

US20090177852A1 DATA BLOCK RECEIVER AND METHOD FOR DECODING DATA BLOCK 审中-公开
标题翻译：数据块接收器和解码数据块的方法
公开(公告)号：US20090177852A1
公开(公告)日：2009-07-09
申请号：US11971233
申请日：2008-01-09
申请人： Chien-yu Chen , Yi-Hung Hsieh
发明人： Chien-yu Chen , Yi-Hung Hsieh
IPC分类号： G06F12/00
CPC分类号： H03M13/2957 , H03M13/6306 , H03M13/6362 , H03M13/6375 , H03M13/6381 , H03M13/658 , H03M13/6588 , H04L1/005 , H04L1/0068 , H04L1/0071 , H04L1/1819
摘要： A data block receiver for decoding a data block. The data block has a block sequence number (BSN). The data block receiver includes two de-interleavers, a memory circuitry, a combiner, a decoder, and an error detector. A first de-interleaver interleaves the data block to obtain a first de-interleaved data block. A stored data block with a BSN same with the data block is retrieved from the memory circuitry when the data block is not the newest data block. The second de-interleaver interleaves the retrieved data block to obtain a second de-interleaved data block. The second and the first de-interleaved data blocks are combined to form a combined data block. The decoder decodes the combined data block. The data block is stored when an error in the decoded data block is detected.
摘要翻译：一种用于解码数据块的数据块接收器。数据块具有块序列号（BSN）。数据块接收器包括两个解交织器，存储器电路，组合器，解码器和误差检测器。第一解交织器交织数据块以获得第一解交织数据块。当数据块不是最新的数据块时，从存储器电路检索具有与数据块相同的BSN的存储的数据块。第二解交织器交织检索的数据块以获得第二解交织数据块。第二和第一解交织数据块被组合以形成组合数据块。解码器解码组合的数据块。当检测到解码数据块中的错误时，存储数据块。

67. 发明授权

US06910171B2 Lossy compression of stakes in turbo decoder 有权
标题翻译： turbo解码器中有害的压缩
公开(公告)号：US06910171B2
公开(公告)日：2005-06-21
申请号：US09945858
申请日：2001-09-04
申请人： Johannus Theodorus Matheus Hubertus Dielissen
发明人： Johannus Theodorus Matheus Hubertus Dielissen
IPC分类号： H03M13/29 , H03M13/39 , H03M13/00
CPC分类号： H03M13/3905 , H03M13/2771 , H03M13/2957 , H03M13/3723 , H03M13/3972 , H03M13/6502 , H03M13/6588
摘要： A turbo decoder employing the sliding window algorithm is computational intensive. Computational requirements are reduced in iterative decoders, at the expense of increased memory usage, by storing the stakes between iterations. The stakes used in this improved sliding windows algorithm can be compressed, resulting in a decoder with minimal additional memory requirements, while retaining the advantages in computational requirements obtained from storing the stakes between iterations.
摘要翻译：采用滑动窗口算法的涡轮解码器是计算密集型的。通过在迭代之间存储桩号，迭代解码器中的计算需求将以增加的内存使用为代价。在这种改进的滑动窗口算法中使用的风险可以被压缩，导致解码器具有最小的附加存储器要求，同时保留从迭代中存储桩之间获得的计算要求中的优点。

68. 发明申请

US20020194567A1 Low complexity channel decoders 有权
标题翻译：低复杂度信道解码器
公开(公告)号：US20020194567A1
公开(公告)日：2002-12-19
申请号：US09880707
申请日：2001-06-12
发明人： Daniel Yellin , Doron Rainish
IPC分类号： H03M013/00
CPC分类号： H03M13/6588 , H03M13/2957 , H03M13/299 , H03M13/3905 , H03M13/6502 , H03M13/6505 , H03M13/6577
摘要： A packet of encoded data is received and decoded using a look-up table that stores information approximating output of an algorithmic decoding process.
摘要翻译：使用存储近似算法解码处理的输出的信息的查找表来接收和解码编码数据的分组。

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