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61. 发明授权

US07688114B2 Ratio asymmetric inverters, and apparatus including one or more ratio asymmetric inverters 失效
标题翻译：比率非对称逆变器和包括一个或多个比例非对称逆变器的装置
公开(公告)号：US07688114B2
公开(公告)日：2010-03-30
申请号：US12121149
申请日：2008-05-15
申请人： Claudio San Roman Denegri
发明人： Claudio San Roman Denegri
IPC分类号： H03K19/094
CPC分类号： H03K19/018514 , H03K5/1515 , H03K2005/00136 , H03M1/0863 , H03M1/742
摘要： A ratio asymmetric inverter has a signal input, signal output, first and second power inputs, pullup and pulldown transistors, and at least one delay element. The pullup transistor has a gate terminal, a source terminal coupled to the first power input, and a drain terminal coupled to the signal output. The pulldown transistor has a gate terminal, a drain terminal coupled to the signal output, and a source terminal coupled to the second power input. The signal input is respectively coupled to the gate terminals of the pullup transistor and the pulldown transistor via first and second signal paths. The at least one delay element is included in only one of the first and second signal paths, to impart a longer propagation delay to the one of the first and second signal paths.
摘要翻译：比例非对称逆变器具有信号输入，信号输出，第一和第二功率输入，上拉和下拉晶体管以及至少一个延迟元件。上拉晶体管具有栅极端子，耦合到第一电力输入端的源极端子和耦合到信号输出端的漏极端子。下拉晶体管具有栅极端子，耦合到信号输出的漏极端子和耦合到第二电力输入端的源极端子。信号输入分别经由第一和第二信号路径耦合到上拉晶体管和下拉晶体管的栅极端子。至少一个延迟元件仅包括在第一和第二信号路径中的一个中，以向第一和第二信号路径中的一个施加更长的传播延迟。

62. 发明申请

US20090108902A1 Delay Circuit Having Reduced Duty Cycle Distortion 有权
标题翻译：具有减少占空比失真的延迟电路
公开(公告)号：US20090108902A1
公开(公告)日：2009-04-30
申请号：US12033567
申请日：2008-02-19
申请人： James D. Chlipala , Scott A. Segan
发明人： James D. Chlipala , Scott A. Segan
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00136 , H03K2005/00234
摘要： A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith.
摘要翻译：提供具有减小的占空比失真的延迟电路。延迟电路包括以串联配置连接在一起的多个延迟元件。每个延迟元件具有与之相关联的规定延迟。延迟电路还包括连接到延迟元件的相应输出的控制器。控制器被配置为使得延迟元件的相应输出和控制器的输出之间的信号路径具有相对于彼此基本相同的延迟。每个信号路径都具有与其相关联的三态开关元件。

63. 发明申请

US20080143410A1 Clock Input/Output Device 审中-公开
标题翻译：时钟输入/输出设备
公开(公告)号：US20080143410A1
公开(公告)日：2008-06-19
申请号：US10566914
申请日：2004-08-04
申请人： Masaki Onishi , Masayu Fujiwara
发明人： Masaki Onishi , Masayu Fujiwara
IPC分类号： H03K3/02
CPC分类号： H03K19/00323 , H03K5/1565 , H03K19/09429 , H03K19/0948 , H03K2005/00136
摘要： A clock input/output device has three-state inverters Iv1 to Iv3 and an inverter Iv4, which cooperate to make equal the on-state resistance through a supply-voltage-side (VDD-side) transistor and the on-state resistance through a ground-voltage-side (0-side) transistor so as to make equal to VDD/2 the threshold voltage with reference to which the clock input/output device evaluates the input thereto to determine whether or not to change the state of the output thereof.
摘要翻译：时钟输入/输出装置具有三态反相器Iv 1至Iv 3和反相器Iv 4，它们协作以使得通过电源电压侧（VDD侧）晶体管等于导通状态电阻和导通状态通过接地电压侧（0侧）晶体管的电阻以使得等于VDD / 2的阈值电压，参考时钟输入/输出装置对其输入进行评估，以确定是否改变其输出。

64. 发明申请

US20080094099A1 Differential line compensation apparatus, method and system 有权
公开(公告)号：US20080094099A1
公开(公告)日：2008-04-24
申请号：US11543009
申请日：2006-10-04
申请人： Ban Hok Goh , Dieter Draxelmayr
发明人： Ban Hok Goh , Dieter Draxelmayr
IPC分类号： H03K19/003
CPC分类号： H03K5/13 , H03K2005/00032 , H03K2005/00045 , H03K2005/00136 , H03L7/0812 , H04L25/0272
摘要： A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

65. 发明授权

US07362129B1 Methods of providing performance compensation for process variations in integrated circuits 有权
标题翻译：为集成电路中的工艺变化提供性能补偿的方法
公开(公告)号：US07362129B1
公开(公告)日：2008-04-22
申请号：US11449198
申请日：2006-06-08
申请人： Arifur Rahman
发明人： Arifur Rahman
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K17/005 , H03K17/302 , H03K17/6872 , H03K19/00384 , H03K19/1737 , H03K2005/00123 , H03K2005/00136
摘要： Methods of compensating for process variations in an integrated circuit. Multiplexer circuits can be programmed to balance the rising and falling delays through the circuits in the presence of process variations. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of PLDs. During wafer sort or final test, a process corner can be determined for each die. One or more E-fuses can be set to predetermined level(s) to program the process corner information into the die, or the values can be stored in some other type of non-volatile memory. The stored values are utilized by the programmable multiplexer circuits to optionally adjust the rising and/or falling delays through the multiplexer circuits to achieve a balance between the rising and falling delays.
摘要翻译：补偿集成电路中工艺变化的方法。可以对多路复用器电路进行编程，以在存在过程变化的情况下平衡通过电路的上升和下降延迟。这些多路复用器电路可以例如用作PLD的互连结构中的可编程互连多路复用器。在晶片分选或最终测试期间，可以确定每个模具的工艺角。可以将一个或多个电子熔丝设置到预定级别以将过程角信息编程到管芯中，或者可以将值存储在某种其他类型的非易失性存储器中。所存储的值被可编程多路复用器电路用于可选地调整通过多路复用器电路的上升和/或下降延迟以实现上升和下降延迟之间的平衡。

66. 发明申请

US20080088365A1 Semiconductor device and method for decreasing noise of output driver 审中-公开
标题翻译：用于降低输出驱动器噪声的半导体器件和方法
公开(公告)号：US20080088365A1
公开(公告)日：2008-04-17
申请号：US11820611
申请日：2007-06-20
申请人： Young-Chan Jang
发明人： Young-Chan Jang
IPC分类号： G06G7/12 , H03K3/00
CPC分类号： H03K5/151 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/1069 , H03K5/13 , H03K2005/00065 , H03K2005/00136
摘要： In a semiconductor device and method for decreasing noise of an output driver block, the semiconductor device monitors differentially amplified voltages output from an output driver block and controls a voltage level at a cross-over point between the differentially amplified voltages so that noise that may be caused by reactance occurring in the output driver block can be removed and so that inter-symbol interference (ISI) that may be caused when a voltage level of a serialized input data is interfered with a voltage level of previously input data can be prevented.
摘要翻译：在用于降低输出驱动器块的噪声的半导体器件和方法中，半导体器件监视从输出驱动器块输出的差分放大电压，并且控制差分放大电压之间的交叉点处的电压电平，使得可以是可以消除在输出驱动器块中发生的电抗引起的，从而可以防止当串行输入数据的电压电平受到先前输入的数据的电压电平时可能引起的符号间干扰（ISI）。

67. 发明申请

US20080088350A1 Duty detector and duty detection/correction circuit including the same and method thereof 有权
标题翻译：负载检测器和占空比检测/校正电路包括其及其方法
公开(公告)号：US20080088350A1
公开(公告)日：2008-04-17
申请号：US11907723
申请日：2007-10-17
申请人： Young-soo Sohn
发明人： Young-soo Sohn
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00136
摘要： A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.
摘要翻译：占空比检测器可以包括第一放大器和/或积分器。第一放大器可以被配置为接收第一信号和互补的第一信号，差分放大第一信号和互补的第一信号，和/或将差分放大的第一信号输出到输出端和差分放大的互补的第一信号信号到互补输出端子。积分器可以连接到第一放大器的输出端和互补输出端，被配置为积分差分放大的第一信号和差分放大的互补第一信号，和/或被配置为输出占空比检测信号。

68. 发明授权

US07190753B2 Method and apparatus for temporally correcting a data signal 有权
标题翻译：时间校正数据信号的方法和装置
公开(公告)号：US07190753B2
公开(公告)日：2007-03-13
申请号：US09947296
申请日：2001-09-05
申请人： Jürgen Zielbauer
发明人： Jürgen Zielbauer
IPC分类号： H04L25/40
CPC分类号： H04L25/242 , G11C7/22 , H03K5/135 , H03K2005/00136 , H04L7/0041 , H04L7/0062 , H04L7/02
摘要： A data signal is detected and compared with a reference value. A displacement time is determined as a function of the difference between the reference value and the signal level of the data signal. The data signal is buffer-stored and output in a manner that is temporally delayed by the displacement time. Accordingly, the data signal has a predetermined value at a predetermined point in time after the buffer-storage. Consequently, the data signal waveform can be defined with respect to time. As a result, a precise signal waveform is prescribed, and time periods for detecting the data signal can be precisely defined.
摘要翻译：检测数据信号并与参考值进行比较。位移时间被确定为参考值与数据信号的信号电平之差的函数。数据信号以时间上延迟移位时间的方式进行缓冲存储和输出。因此，数据信号在缓冲存储之后的预定时间点具有预定值。因此，可以相对于时间来定义数据信号波形。结果，规定了精确的信号波形，并且可以精确地定义用于检测数据信号的时间段。

69. 发明授权

US07038513B2 Closed-loop independent DLL-controlled rise/fall time control circuit 失效
公开(公告)号：US07038513B2
公开(公告)日：2006-05-02
申请号：US10878033
申请日：2004-06-29
申请人： Timothy M. Wilson , Michael C. Rifani , Songmin Kim , Greg Taylor , Navindra Navaratnam
发明人： Timothy M. Wilson , Michael C. Rifani , Songmin Kim , Greg Taylor , Navindra Navaratnam
IPC分类号： H03K5/12
CPC分类号： H03K19/00323 , H03K5/023 , H03K2005/00136 , H03L7/0812 , H04L25/0288
摘要： A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

70. 发明申请

US20050285648A1 Closed-loop independent DLL-controlled rise/fall time control circuit 失效
标题翻译：闭环独立DLL控制上升/下降时间控制电路
公开(公告)号：US20050285648A1
公开(公告)日：2005-12-29
申请号：US10878033
申请日：2004-06-29
申请人： Timothy Wilson , Michael Rifani , Songmin Kim , Greg Taylor , Navindra Navaratnam
发明人： Timothy Wilson , Michael Rifani , Songmin Kim , Greg Taylor , Navindra Navaratnam
IPC分类号： H03K5/00 , H03K5/02 , H03K19/003 , H03L7/06 , H03L7/081 , H04L25/02
CPC分类号： H03K19/00323 , H03K5/023 , H03K2005/00136 , H03L7/0812 , H04L25/0288
摘要： A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.
摘要翻译：用于处理信号的系统和方法确定驱动信号的上升和下降时间，将上升和下降时间与期望值进行比较，并且独立地将上升和下降时间控制为等于期望值。上升和下降时间可以通过基于上升时间和所需值之间的差异产生一个或多个第一校正位来控制，基于下降时间和下降时间之间的差产生一个或多个第二校正位对应一个期望值，然后分别施加位以独立地控制驱动信号的上升和下降时间。驱动信号可以是I / O信号或其他类型的信号。

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