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61. 发明授权

US06459338B1 Single loop output common mode feedback circuit for high performance class AB differential amplifier 有权
标题翻译：用于高性能AB类差分放大器的单回路输出共模反馈电路
公开(公告)号：US06459338B1
公开(公告)日：2002-10-01
申请号：US09863692
申请日：2001-05-23
申请人： Julio E. Acosta , Kambiz Hayat-Dawoodi
发明人： Julio E. Acosta , Kambiz Hayat-Dawoodi
IPC分类号： H03F345
CPC分类号： H03F3/45094 , H03F3/45152 , H03F3/45511 , H03F2203/45402 , H03F2203/45418 , H03F2203/45458 , H03F2203/45612 , H03F2203/45711
摘要： A class AB input differential amplifier employs a single loop output common mode feedback circuit (CMFC) to achieve high performance by controlling the common mode output voltage. The CMFC includes a small amplifier to compare the common mode voltage at the output with a desired voltage specified at the common mode output voltage pin. Having only one loop to control this voltage instead of two makes the design more reliable and easier to compensate since there is no need to worry about how multiple loops will interact.
摘要翻译： AB类输入差分放大器采用单回路输出共模反馈电路（CMFC），通过控制共模输出电压实现高性能。 CMFC包括一个小型放大器，用于将输出端的共模电压与共模输出电压引脚上规定的所需电压进行比较。只有一个环路来控制这个电压而不是两个电路使得设计更加可靠和更容易补偿，因为不需要担心多个环路如何交互。

62. 发明申请

US20020135403A1 Trigger circuit 审中-公开
标题翻译：触发电路
公开(公告)号：US20020135403A1
公开(公告)日：2002-09-26
申请号：US09873789
申请日：2001-06-04
发明人： Syed K. Enam , Masoud Djafari , R. Kent Smythe
IPC分类号： H03K003/00
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that provide high-speed current pulses. In one embodiment, the trigger circuit provides a current sink pulse as an output. One embodiment of the trigger circuit includes a first input transistor and an output transistor that are emitter coupled to a common resistor. A collector of the first input transistor is alternating current (AC) coupled to a base of the output transistor to drive the output transistor. Advantageously, the AC coupling allows the first input transistor to powerfully drive the output transistor during logic state transitions and yet maintain a low average current. The resistor coupled to the emitter of the first input transistor and the emitter of the output transistor advantageously provides positive feedback or hysteresis feedback, thereby further enhancing the response of the trigger circuit.
摘要翻译：本发明涉及提供高速电流脉冲的方法和装置。在一个实施例中，触发电路提供电流吸收脉冲作为输出。触发电路的一个实施例包括发射极耦合到公共电阻器的第一输入晶体管和输出晶体管。第一输入晶体管的集电极是耦合到输出晶体管的基极以驱动输出晶体管的交流电（AC）。有利地，AC耦合允许第一输入晶体管在逻辑状态转变期间强力地驱动输出晶体管，并且保持低的平均电流。耦合到第一输入晶体管的发射极和输出晶体管的发射极的电阻有利地提供正反馈或滞后反馈，从而进一步增强触发电路的响应。

63. 发明申请

US20020122443A1 Data transition identifier 审中-公开
标题翻译：数据转换标识符
公开(公告)号：US20020122443A1
公开(公告)日：2002-09-05
申请号：US09873793
申请日：2001-06-04
发明人： Syed K. Enam , Masoud Djafari , R. Kent Smythe
IPC分类号： H04J003/02
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that indicate a first logic state and a second logic state associated with consecutive bits in a serial bitstream of a relatively high-frequency network. The serial bitstream is demultiplexed to retrieve the consecutive bits, and the consecutive bits are provided as inputs to an identifier circuit. The identifier circuit receives the demultiplexed consecutive bits and indicates via balanced outputs whether consecutive bits of the serial bitstream corresponded to logic 0 to logic 0, logic 0 to logic 1, logic 1 to logic 0, or logic 1 to logic 1. The balanced outputs that indicate the logic 0 to logic 0 sequence, the logic 0 to logic 1 sequence, the logic 1 to logic 0 sequence, and the logic 1 to logic 1 sequence advantageously provide matched delays from an activation of the identifier circuit to the activation of one of the balanced outputs.
摘要翻译：本发明涉及指示与相对高频网络的串行比特流中的连续比特相关联的第一逻辑状态和第二逻辑状态的方法和装置。串行比特流被解复用以检索连续比特，并且连续比特被提供给标识符电路的输入。标识符电路接收经解复用的连续位，并通过平衡输出指示串行比特流的连续比特是否对应于逻辑0到逻辑0到逻辑0到逻辑1，逻辑1到逻辑1或逻辑1到逻辑1.平衡输出指示逻辑0到逻辑0序列，逻辑0到逻辑1序列，逻辑1到逻辑0序列，逻辑1到逻辑1序列有利地提供从标识符电路的激活到激活一个的平衡输出。

64. 发明申请

US20020122438A1 Current mode phase detection 审中-公开
标题翻译：电流模式相位检测
公开(公告)号：US20020122438A1
公开(公告)日：2002-09-05
申请号：US09873939
申请日：2001-06-04
发明人： Syed K. Enam , Masoud Djafari , R. Kent Smythe
IPC分类号： H04J003/06
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to phase detectors that integrate a portion of a transition between adjacent or consecutive bits of a serial bitstream in a relatively fixed window by switching currents as opposed to voltages. The phase detector can be used to synchronize a VCO clock in a PLL to a fast data bitstream used in an optical network, such as SONET. Advantageously, embodiments of a current mode phase detector switch currents, rather than voltages, to integrate the window of the serial bitstream. The current switching allows devices to operate at frequencies approaching the device's fT and can advantageously extend the phase detector's bandwidth and allow an associated transceiver to operate at higher data rates. By contrast, the conventional switching of voltage results in a delay induced by the charging of related capacitances, such as parasitic substrate capacitances, which in turn results in actual performance far below the fT of the devices.
摘要翻译：本发明涉及相位检测器，其通过与电压相反的开关电流将相对固定的窗口中的串行位流的相邻位或连续位之间的转变的一部分进行积分。相位检测器可用于将PLL中的VCO时钟同步到光网络（如SONET）中使用的快速数据位流。有利地，电流模式相位检测器的实施例开关电流而不是电压以集成串行比特流的窗口。当前的切换允许设备在接近设备的fT的频率下操作，并且可以有利地扩展相位检测器的带宽并允许相关收发器以更高的数据速率工作。相比之下，常规的电压切换导致由相关电容的充电引起的延迟，例如寄生衬底电容，这进而导致实际性能远低于器件的fT。

65. 发明申请

US20020118704A1 Acquisition aid circuit 审中-公开
标题翻译：采集辅助电路
公开(公告)号：US20020118704A1
公开(公告)日：2002-08-29
申请号：US09873950
申请日：2001-06-04
发明人： Syed K. Enam , Masoud Djafari , R. Kent Smythe , Michael B. Choi , Vi Lee
IPC分类号： H04J003/06
CPC分类号： H04L7/0338 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0047 , H03F3/45085 , H03F2203/45592 , H03F2203/45612 , H03K19/01812 , H03L7/085 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/099 , H03L7/10 , H03L7/14 , H03L7/18 , H03L2207/06 , H04J3/0608 , H04L1/242 , H04L7/0008 , H04L7/033 , H04L7/0337 , H04L25/0266 , H04L25/0272 , H04L25/0274 , H04L25/0278 , H04L25/028 , H04L25/0282 , H04L25/0286 , H04L25/0292 , H04L25/0294 , H04L25/05
摘要： The invention relates to methods and apparatus that compare the frequencies of a first clock signal and a second clock signal and reliably provide an indication of whether the frequency relationship between the first clock signal and the second clock signal is within a predetermined range. In one embodiment, the first clock signal is a reference clock signal and the second clock signal is generated from a serial bitstream. The indication can be used to synchronize a voltage controlled oscillator within a phase locked loop to the reference clock signal to thereby keep the phase locked loop within a lock range of a serial bitstream from which the second clock is generated. Embodiments of the invention digitally generate a beat frequency related to a difference in speed between the first clock signal and the second clock signal. The beat frequency is synchronized, advantageously obviating the need to synchronize asynchronous counters as is conventionally done.
摘要翻译：本发明涉及比较第一时钟信号和第二时钟信号的频率并可靠地提供第一时钟信号和第二时钟信号之间的频率关系是否在预定范围内的指示的方法和装置。在一个实施例中，第一时钟信号是参考时钟信号，并且第二时钟信号是从串行比特流产生的。该指示可以用于将锁相环内的压控振荡器与参考时钟信号同步，从而将锁相环保持在产生第二时钟的串行比特流的锁定范围内。本发明的实施例数字地产生与第一时钟信号和第二时钟信号之间的速度差相关的拍频。节拍频率是同步的，有利地消除了如以往所做同步异步计数器的需要。

66. 发明申请

US20020075074A1 Differential amplifier with large input common mode signal range 失效
标题翻译：差分放大器具有大输入共模信号范围
公开(公告)号：US20020075074A1
公开(公告)日：2002-06-20
申请号：US10015887
申请日：2001-12-17
申请人： Broadcom Corporation
发明人： Hongwei Wang , Ardie Venes
IPC分类号： H03F003/45
CPC分类号： H03F3/72 , H03F3/45183 , H03F3/4521 , H03F3/45708 , H03F2203/45371 , H03F2203/45612 , H03F2203/7203
摘要： A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two amplifying MOSFETs. A source follower is connected to the gate terminal of each amplifying MOSFET in one of the differential pairs. A differential signal applied to the differential amplifier comprises two separate signal. Each separate signal is applied to the gate terminals of both the amplifying MOSFET in the differential pair not driven by the source follower and the driven MOSFET of the source follower. The differential amplifier further comprises a pair of switch MOSFETs connected to a current source MOSFET. The switch MOSFETs act to control the distribution of the total current flowing from the current source MOSFET and, consequently, to determine which differential pair works dominantly to amplify the input signals. Each source follower acts to offset the voltage of its input signal to compensate for the range loss due to the bias voltages and the threshold voltages within the differential amplifier.
摘要翻译：具有大输入共模信号范围的差分放大器的设计。差分放大器包括两个差分对，每个具有两个放大MOSFET。源极跟随器连接到差分对之一中每个放大MOSFET的栅极端子。施加到差分放大器的差分信号包括两个单独的信号。每个单独的信号被施加到不由源极跟随器和源极跟随器的驱动MOSFET驱动的差分对中的放大MOSFET的栅极端子。差分放大器还包括连接到电流源MOSFET的一对开关MOSFET。开关MOSFET用于控制从电流源MOSFET流出的总电流的分布，并因此确定哪个差分对主要工作以放大输入信号。每个源极跟随器用于抵消其输入信号的电压，以补偿差分放大器内的偏置电压和阈值电压引起的范围损耗。

67. 发明授权

US06396430B1 Pre-amplifier design for high-speed analog-to-digital converters 有权
标题翻译：用于高速模数转换器的前置放大器设计
公开(公告)号：US06396430B1
公开(公告)日：2002-05-28
申请号：US09929759
申请日：2001-08-14
申请人： Qunying Li
发明人： Qunying Li
IPC分类号： H03M110
CPC分类号： H03M1/1023 , H03F3/45977 , H03F2203/45511 , H03F2203/45534 , H03F2203/45612 , H03F2203/45616
摘要： The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. The circuit and method employ an input offset storage (IOS) technique to calibrate the differential comparator device during an auto-zero cycle. The reference voltage and offset voltages are stored on capacitors coupled to the inputs of the differential comparator device during the auto-zero cycle. A source follower is placed between each capacitor and the inputs to the differential comparator device. The source followers are selected to prevent leakage from the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the capacitors in the conversion mode.
摘要翻译：本发明克服了先进的CMOS技术中存在的栅极泄漏缺点，以实现极高速的模数转换。电路和方法采用输入偏移存储（IOS）技术来在自动归零周期期间校准差分比较器器件。在自动归零周期期间，参考电压和偏移电压存储在耦合到差分比较器器件的输入端的电容器上。源极跟随器位于每个电容器和差分比较器器件的输入端之间。选择源跟随器以防止在转换模式期间从电容器泄漏。此外，还选择用于自动归零差分比较器的反馈回路中的开关，以防止转换模式下电容器的泄漏。

68. 发明申请

US20020053948A1 Low voltage rail-to-rail CMOS input stage 有权
公开(公告)号：US20020053948A1
公开(公告)日：2002-05-09
申请号：US10013581
申请日：2001-12-10
发明人： Troy L. Stockstad
IPC分类号： H03F003/45
CPC分类号： H03F3/45192 , H03F2203/45342 , H03F2203/45612
摘要： The present invention discloses a low voltage rail-to-rail CMOS input stage. The input stage includes a differential pail of P-channel metal oxide semiconductor field effect (PMOS) transistors, which produces differential output current signal. The input stage further includes a pair of N-channel depletion-mode metal oxide semiconductor field effect (NMOS) transistors, coupled to the bulk terminals of the differential pair of PMOS transistors, for receiving an input signal. The depletion-mode NMOS transistors further act as source follower devices to drive the bulk terminals of the differential pair of PMOS transistors.

69. 发明授权

US06317001B1 Compensation of timing errors caused by dynamic thermal mismatch 失效
标题翻译：由动态热失配引起的定时误差的补偿
公开(公告)号：US06317001B1
公开(公告)日：2001-11-13
申请号：US09453187
申请日：1999-12-02
申请人： Bernhard Roth
发明人： Bernhard Roth
IPC分类号： H03F304
CPC分类号： H03F3/45085 , H03F1/302 , H03F3/456 , H03F2200/531 , H03F2203/45511 , H03F2203/45612 , H03F2203/45702 , H03K19/00376
摘要： Disclosed is a compensation circuit for compensating a change in timing information of an input signal caused by thermal variations in a first circuit. The first circuit comprises one or more devices each having a temperature dependent on the input signal. Accordingly, the compensation circuit comprises one or more compensation devices each having a temperature dependent on the input signal. The compensation circuit is connected in series with the first circuit and the series connection receives the input signal and provides a timing-compensated output signal with substantially the same timing information as of the input signal. The thermal characteristic of at least one of the one or more compensation devices is proportional or in some other known relation to a corresponding one of the one or more devices of the first circuit. The compensation circuit provides a compensation output signal having substantially opposite or inverse thermal distortions than the first circuit.
摘要翻译：公开了一种补偿电路，用于补偿由第一电路中的热变化引起的输入信号的定时信息的变化。第一电路包括一个或多个装置，每个装置具有取决于输入信号的温度。因此，补偿电路包括一个或多个补偿装置，每个补偿装置具有取决于输入信号的温度。补偿电路与第一电路串联连接，串联连接接收输入信号，并提供与输入信号基本相同的定时信息的定时补偿输出信号。一个或多个补偿装置中的至少一个补偿装置的热特性与第一电路的一个或多个装置中的对应的一个成比例或一些其它已知的关系。补偿电路提供具有与第一电路基本上相反或相反的热失真的补偿输出信号。

70. 发明授权

US06275108B1 Circuit and method for control of amplifier operating angle 有权
标题翻译：用于控制放大器工作角度的电路和方法
公开(公告)号：US06275108B1
公开(公告)日：2001-08-14
申请号：US09525995
申请日：2000-03-15
申请人： Clyde Washburn
发明人： Clyde Washburn
IPC分类号： H03F345
CPC分类号： H03F3/265 , H03F1/0261 , H03F3/45183 , H03F2203/30084 , H03F2203/30117 , H03F2203/45612 , H03F2203/45622
摘要： A method and apparatus for controlling amplifier operating angle provides a corresponding increase in amplifier efficiency through a continual adjustment of operating angle from Class A, through Class AB, to Class B, an improved bandwidth in the output stage by preventing the output stage from reaching cutoff and the ability to adjust the high frequency content of the drive waveform to match that of the output stage thereby attaining the highest efficiency consistent with required distortion levels. A push-pull amplifier is coupled to a differential pushpull current drive source with out of phase drive signals and a preprocessing circuit with a first set of current sources which mirror one drive signal and a second set of current sources which mirror the other drive signal. The preprocessing circuit provides a full-wave rectified signal substantially representing the combined lower halves of the out of phase drive signals to be summed with the drive signals as composite input waveforms for the push-pull amplifier. The rectified signal is common-mode to both sides of the amplifier and gives instantaneous control of the bias point such that it is always just large enough to support the instantaneous amplitude of the signals as it adjusts the operating angle of the push-pull amplifier from Class A through Class B. A transformer is coupled to the output stages of the push-pull amplifier for summing the output signals.
摘要翻译：用于控制放大器操作角度的方法和装置通过将工作角度从A类，通过AB类连续调整到B类来提供放大器效率的相应增加，通过防止输出级达到截止，在输出级中改善带宽以及调整驱动波形的高频内容以匹配输出级的能力的能力，从而获得与所需失真水平一致的最高效率。推挽放大器耦合到具有异相驱动信号的差分推挽电流驱动源，以及具有第一组电流源的预处理电路，该第一组电流源将一个驱动信号和第二组电流源镜像到另一个驱动信号。预处理电路提供基本上表示与驱动信号相加的异相驱动信号的组合下半部分的全波整流信号，作为推挽放大器的复合输入波形。整流信号在放大器的两侧是共模的，并给出了偏置点的瞬时控制，使得它总是足够大，以支持信号的瞬时幅度，因为它调整推挽放大器的工作角度 A类到B类。变压器耦合到推挽放大器的输出级，用于对输出信号求和。

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