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61. 发明授权

US09793342B2 Insulated gate type semiconductor device and method for fabricating the same 有权
公开(公告)号：US09793342B2
公开(公告)日：2017-10-17
申请号：US14976873
申请日：2015-12-21
申请人： RENESAS ELECTRONICS CORPORATION , RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.
发明人： Hiroshi Inagawa , Nobuo Machida , Kentaro Oishi
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/739 , H01L29/423 , H01L29/51 , H01L29/417
CPC分类号： H01L29/7808 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/511 , H01L29/66333 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/7821 , H01L29/7827
摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

62. 发明申请

US20170229536A1 POWER DEVICE ON BULK SUBSTRATE 审中-公开
公开(公告)号：US20170229536A1
公开(公告)日：2017-08-10
申请号：US15494399
申请日：2017-04-21
申请人： Silanna Asia Pte Ltd
发明人： Michael A. Stuber , Stuart B. Molin , Jacek Korec , Boyi Yang
IPC分类号： H01L29/06 , H01L29/78 , H01L29/73 , H01L29/739 , H01L29/10 , H01L29/872 , H01L29/8605 , H01L29/94 , H01L21/8249 , H01L29/49 , H01L29/40 , H01L29/861
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/0688 , H01L29/1008 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/6625 , H01L29/66265 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/7313 , H01L29/7317 , H01L29/735 , H01L29/7391 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/945 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

63. 发明授权

US09412881B2 Power device integration on a common substrate 有权
公开(公告)号：US09412881B2
公开(公告)日：2016-08-09
申请号：US13939451
申请日：2013-07-11
申请人： Silanna Asia Pte Ltd.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L27/06 , H01L29/872 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/40 , H01L29/06 , H01L29/94 , H01L29/36 , H01L29/73 , H01L29/735 , H01L29/8605 , H01L29/861 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/10
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

64. 发明授权

US09349830B2 Semiconductor element and manufacturing method and operating method of the same 有权
标题翻译：半导体元件及其制造方法和操作方法相同
公开(公告)号：US09349830B2
公开(公告)日：2016-05-24
申请号：US13784886
申请日：2013-03-05
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Wing-Chor Chan , Hsin-Liang Chen
IPC分类号： H01L29/00 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/74 , H01L29/749 , H01L29/861 , H01L27/02 , H01L29/423 , H01L29/08
CPC分类号： H01L29/66477 , H01L27/027 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816 , H01L29/7821 , H01L29/7835 , H01L29/861
摘要： A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.
摘要翻译：提供半导体元件及其制造方法及其操作方法。半导体元件包括衬底，第一阱，第一重掺杂区，至少第二重掺杂区，栅极层，第三重掺杂区和第四重掺杂区。第一阱和第三重掺杂区域设置在衬底上。第一和第四重掺杂区域设置在第一阱中。第二重掺杂区域设置在第一重掺杂区域中。栅极层设置在第一阱上。具有第一类型掺杂的第一，第三和第四重掺杂区彼此分离。第一阱和第二重掺杂区域具有与第一类型掺杂互补的第二类型掺杂。

65. 发明申请

US20150147855A1 SEMICONDUCTOR DEVICE WITH HIGH BREAKDOWN VOLTAGE AND MANUFACTURE THEREOF 有权
标题翻译：具有高断路电压和制造的半导体器件
公开(公告)号：US20150147855A1
公开(公告)日：2015-05-28
申请号：US14614795
申请日：2015-02-05
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Kazuhiko Takada
IPC分类号： H01L21/8234 , H01L21/265 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823493 , H01L21/265 , H01L27/0629 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0873 , H01L29/42368 , H01L29/456 , H01L29/66106 , H01L29/66484 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7821 , H01L29/7835 , H01L29/866
摘要： A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.
摘要翻译：半导体器件包括：在p型半导体衬底中形成的第一和第二n型阱，第二n型阱比第一n型阱更深; 形成在第一和第二n型孔中的第一和第二p型背栅区; 形成在第一和第二p型背栅区域中的第一和第二n型源极区域; 第一和第二n型漏极区，形成在第一和第二n型阱中，与第一和第二n型源极区相对的位置，夹持第一和第二p型背栅区; 以及在所述第一和第二p型背栅区与所述第一和第二n型漏极区之间的位置处形成在所述衬底上的场绝缘膜; 由此在第一n型阱中形成第一晶体管，并且在具有比第一晶体管更高的反向电压耐久性的第二n型阱中形成第二晶体管。

66. 发明授权

US08981476B2 Semiconductor device with high breakdown voltage and manufacture thereof 有权
标题翻译：具有高击穿电压的半导体器件及其制造
公开(公告)号：US08981476B2
公开(公告)日：2015-03-17
申请号：US13710837
申请日：2012-12-11
申请人： Fujitsu Semiconductor Limited
发明人： Kazuhiko Takada
IPC分类号： H01L29/66 , H01L27/06 , H01L29/78 , H01L29/08 , H01L29/423 , H01L29/45 , H01L29/866 , H01L29/06
CPC分类号： H01L21/823493 , H01L21/265 , H01L27/0629 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0873 , H01L29/42368 , H01L29/456 , H01L29/66106 , H01L29/66484 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7821 , H01L29/7835 , H01L29/866
摘要： A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.
摘要翻译：半导体器件包括：在p型半导体衬底中形成的第一和第二n型阱，第二n型阱比第一n型阱更深; 形成在第一和第二n型孔中的第一和第二p型背栅区; 形成在第一和第二p型背栅区域中的第一和第二n型源极区域; 第一和第二n型漏极区，形成在第一和第二n型阱中，与第一和第二n型源极区相对的位置，夹持第一和第二p型背栅区; 以及在所述第一和第二p型背栅区与所述第一和第二n型漏极区之间的位置处形成在所述衬底上的场绝缘膜; 由此在第一n型阱中形成第一晶体管，并且在具有比第一晶体管更高的反向电压耐久性的第二n型阱中形成第二晶体管。

67. 发明申请

US20140291762A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
公开(公告)号：US20140291762A1
公开(公告)日：2014-10-02
申请号：US14305632
申请日：2014-06-16
申请人： IO Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L29/872 , H01L29/78
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

68. 发明申请

US20140110780A1 INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：US20140110780A1
公开(公告)日：2014-04-24
申请号：US14143196
申请日：2013-12-30
申请人： Renesas Eastern Japan Semiconductor, Inc. , Renesas Electronics Corporation
发明人： Hiroshi INAGAWA , Nobuo MACHIDA , Kentaro OISHI
IPC分类号： H01L29/78
CPC分类号： H01L29/7808 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/511 , H01L29/66333 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/7821 , H01L29/7827
摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
摘要翻译：在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

69. 发明授权

US08471337B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08471337B2
公开(公告)日：2013-06-25
申请号：US13073755
申请日：2011-03-28
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/94
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：公开了一种集成电路，其具有包括第一p型区域和与第一p型区域邻接的第一n型区域的半导体部件，其一起形成具有击穿电压的第一pn结。提供了与第一p型区域相邻的另一个n型区域或与第一n型区域相邻的另外的p型区域，第一p型或n型区域和另外的n型或p型区域区域相邻的区域一起形成具有另外的击穿电压的另外的pn结，第一pn结和另外的pn结彼此连接或连接，使得在半导体部件的过载的情况下，考虑到当前负载的第一个pn结，首先进一步的pn结分解。

70. 发明申请

US20130137223A1 INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 失效
公开(公告)号：US20130137223A1
公开(公告)日：2013-05-30
申请号：US13747557
申请日：2013-01-23
申请人： Renesas Electronics Corporation , Hitachi Tobu Semiconductor, Ltd.
发明人： Hiroshi INAGAWA , Nobuo MACHIDA , Kentaro OISHI
IPC分类号： H01L29/66
CPC分类号： H01L29/7808 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/511 , H01L29/66333 , H01L29/66348 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/7821 , H01L29/7827
摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

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