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61. 发明授权

US09343300B1 Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region 有权
标题翻译：形成具有含锗沟道区的PMOS晶体管器件的源极/漏极区域的方法
公开(公告)号：US09343300B1
公开(公告)日：2016-05-17
申请号：US14686857
申请日：2015-04-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Ajey Poovannummoottil Jacob , Michael Hargrove , Jody A. Fronheiser , Murat Kerem Akarvardar
IPC分类号： H01L21/336 , H01L21/02 , H01L29/66 , H01L21/324 , H01L29/167 , H01L21/311 , H01L21/8234 , H01L21/225
CPC分类号： H01L29/66636 , H01L21/02579 , H01L21/02694 , H01L21/2251 , H01L21/2257 , H01L21/823418 , H01L21/823431 , H01L29/165 , H01L29/66553 , H01L29/66795 , H01L29/7848
摘要： The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.
摘要翻译：本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

62. 发明授权

US09306010B2 Semiconductor arrangement 有权
标题翻译：半导体安排
公开(公告)号：US09306010B2
公开(公告)日：2016-04-05
申请号：US13419469
申请日：2012-03-14
申请人： Hans-Joachim Schulze , Manfred Kotek , Johannes Baumgartl , Markus Harfmann , Christian Krenn , Thomas Neidhart
发明人： Hans-Joachim Schulze , Manfred Kotek , Johannes Baumgartl , Markus Harfmann , Christian Krenn , Thomas Neidhart
IPC分类号： H01L29/207 , H01L29/66 , H01L29/78 , H01L29/161 , H01L29/167 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/20
CPC分类号： H01L29/7802 , H01L21/2251 , H01L21/3247 , H01L21/6835 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/2003 , H01L29/207 , H01L29/66712 , H01L2221/68345
摘要： A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.
摘要翻译：第一导电类型的第一半导体区域由掺杂有第一和第二掺杂剂的半导体基底材料形成。第一和第二掺杂剂是不同的物质，也不同于半导体基材。第一掺杂剂是电活性的并且引起半导体基底材料中的第一导电类型的掺杂，并且导致纯的未掺杂的第一半导体区域的晶格常数的减小或增加。第二掺杂剂可以是电活性的，并且可以具有与第一掺杂剂相同的掺杂类型，导致第一半导体区的硬化; 如果第一掺杂剂引起降低，则纯的未掺杂的第一半导体区域的晶格常数增加，并且如果第一掺杂剂分别引起增加，则纯的未掺杂的第一半导体区域的晶格常数降低。

63. 发明申请

US20160093618A1 SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING NFET SEMICONDUCTOR FINS AND PFET SEMICONDUCTOR FINS 有权
标题翻译：用于整合NFET半导体FINS和PFET半导体FINS的单源/漏极外延
公开(公告)号：US20160093618A1
公开(公告)日：2016-03-31
申请号：US14496815
申请日：2014-09-25
申请人： International Business Machines Corporation
发明人： Hemanth Jagannathan , Alexander Reznicek
IPC分类号： H01L27/092 , H01L29/161 , H01L29/167 , H01L29/66 , H01L21/8258 , H01L21/8238 , H01L21/225 , H01L21/324 , H01L29/06 , H01L29/20
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/2251 , H01L21/2258 , H01L21/324 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/8258 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0653 , H01L29/161 , H01L29/167 , H01L29/20 , H01L29/207 , H01L29/66545 , H01L29/6681 , H01L29/7848
摘要： A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.
摘要翻译：跨越从半导体衬底的表面向上延伸的nFET半导体鳍片和pFET半导体鳍片形成多个栅极结构。硼掺杂的硅锗合金材料从nFET半导体鳍片和不被栅极结构保护的pFET半导体鳍片的暴露表面外延生长。然后进行退火。在退火期间，来自硼掺杂硅锗合金材料的硅和锗扩散到nFET半导体鳍片中，并且用作在nFET半导体鳍片中形成结的n型掺杂剂。由于硼是IIIA族元素，因此它没有任何不利影响。在相同退火期间，来自硼掺杂硅锗合金材料的硼将扩散到pFET半导体鳍片中以在其中形成结。

64. 发明申请

US20150364577A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20150364577A1
公开(公告)日：2015-12-17
申请号：US14710536
申请日：2015-05-12
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takeyoshi NISHIMURA , Shun YAMAGUCHI , Toshiaki SAKATA
IPC分类号： H01L29/66 , H01L21/265 , H01L21/324 , H01L21/225 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66712 , H01L21/2251 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/66734 , H01L29/7811
摘要： A method of manufacturing a semiconductor device includes forming a first parallel pn layer; depositing a first-conductivity-type first semiconductor layer on a surface of the first parallel pn layer in a step that further includes forming a second parallel pn layer by selectively introducing second-conductivity-type impurities into the first semiconductor layer; and forming first second-conductivity-type impurity regions in positions opposed in a depth direction to regions of the first parallel pn layer in which second-conductivity-type semiconductor regions are formed; and forming a local insulating film on a surface of the first semiconductor layer in a termination structure portion so that an end portion of the local insulating film is positioned on the first second-conductivity-type impurity region, by heating at a low temperature effective to suppress diffusion of the first second-conductivity-type impurity regions. The method may further include diffusing the first second conductivity type impurity regions in a second heat treatment.
摘要翻译：一种制造半导体器件的方法包括：形成第一平行pn层; 在第一并联pn层的表面上沉积第一导电型第一半导体层，该步骤还包括通过选择性地将第二导电型杂质引入到第一半导体层中而形成第二平行pn层; 以及在深度方向上与形成有第二导电型半导体区域的第一并联pn层的区域形成第一第二导电型杂质区域; 以及在终端结构部分的第一半导体层的表面上形成局部绝缘膜，使得局部绝缘膜的端部位于第一第二导电型杂质区上，通过在有效至抑制第一第二导电型杂质区的扩散。该方法还可以包括在第二热处理中扩散第一第二导电类型杂质区。

65. 发明申请

US20150255481A1 Metal Replacement Process For Low Resistance Source Contacts In 3D NAND 有权
标题翻译：金属替代工艺用于3D NAND中的低电阻源触点
公开(公告)号：US20150255481A1
公开(公告)日：2015-09-10
申请号：US14200426
申请日：2014-03-07
申请人： SanDisk Technologies Inc.
发明人： Matthias Baenninger , Johann Alsmeier , Akira Matsudaira , Jayavel Pachamuthu
IPC分类号： H01L27/115 , H01L21/225 , H01L21/28 , H01L21/02 , H01L21/311 , H01L29/66 , H01L21/306
CPC分类号： H01L21/28282 , H01L21/02587 , H01L21/2251 , H01L21/306 , H01L21/31111 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66666 , H01L29/66833
摘要： A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.
摘要翻译：为3D堆叠的非易失性存储器件提供制造工艺，其提供源极接触到堆叠底部的存储器孔。堆叠包括在衬底上的交替的控制栅极层和介电层，并且通过堆叠蚀刻存储器孔。该过程避免了在存储器孔的底部蚀刻通过膜的需要。相反，从存储孔的底部到堆叠的顶部形成路径。路径包括使用衬底电介质中的空隙沟槽的水平部分和在堆叠中蚀刻的通道。记忆膜，通道材料和电介质材料同时沉积在空隙和存储孔的整个内表面中。该路径被填充金属以形成连续的低电阻导电路径。

66. 发明申请

US20150243739A1 Doping for FinFET 有权
标题翻译：掺杂FinFET
公开(公告)号：US20150243739A1
公开(公告)日：2015-08-27
申请号：US14186910
申请日：2014-02-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Kai Chen , Tsung-Hung Lee , Han-Pin Chung , Shih-Syuan Huang , Chun-Fu Cheng , Chien-Tai Chan , Kuang-Yuan Hsu , Hsien-Chin Lin , Ka-Hing Fung
IPC分类号： H01L29/36 , H01L29/06 , H01L21/225 , H01L29/78
CPC分类号： H01L21/2251 , H01L21/2255 , H01L21/823821 , H01L21/845 , H01L29/0657 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/7851
摘要： First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.
摘要翻译：从基板形成第一和第二散热片。第一层形成在第一鳍上。第一层包括第一掺杂剂。第一层的一部分从第一鳍片的尖端部分去除。第二层形成在第二鳍上。第二层包括第二掺杂剂。第一和第二掺杂剂之一是p型掺杂剂，第一和第二掺杂剂中的另一种是n型掺杂剂。第二层的一部分从第二鳍的尖端部分移除。执行固相扩散处理以将第一掺杂剂扩散到第一鳍片的非尖端部分中，并将第二掺杂剂扩散到第二鳍片的非尖端部分。

67. 发明申请

US20150206972A1 METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER 审中-公开
公开(公告)号：US20150206972A1
公开(公告)日：2015-07-23
申请号：US14675156
申请日：2015-03-31
申请人： STMICROELECTRONICS, INC.
发明人： QING LIU , NICOLAS LOUBET
IPC分类号： H01L29/78 , H01L21/84 , H01L21/225 , H01L21/8238 , H01L27/12 , H01L27/092
CPC分类号： H01L29/7849 , H01L21/02532 , H01L21/2251 , H01L21/7624 , H01L21/76264 , H01L21/76283 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/4908 , H01L29/66742 , H01L29/7842 , H01L29/7848
摘要： A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

68. 发明申请

US20150206875A1 FinFET Semiconductor Device with Germanium Diffusion Over Silicon Fins 有权
标题翻译：具有锗扩散的FinFET半导体器件
公开(公告)号：US20150206875A1
公开(公告)日：2015-07-23
申请号：US14158547
申请日：2014-01-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L27/088 , H01L21/324 , H01L21/02 , H01L29/161 , H01L29/165 , H01L29/16 , H01L21/8234
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/2251 , H01L21/30625 , H01L21/3065 , H01L21/324 , H01L21/823412 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/66818 , H01L29/7851 , H01L29/7854
摘要： A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.
摘要翻译：一种半导体装置的制造方法，其特征在于，包括：提供基板，形成具有第一半导体材料的多个散热片，用第二半导体材料代替至少一个所述散热片的第一部分，将所述第二半导体材料从所述第一部分到所述至少一个所述翅片的第二部分。

69. 发明申请

US20150123193A1 SGT-INCLUDING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： SGT-包括半导体器件及其制造方法
公开(公告)号：US20150123193A1
公开(公告)日：2015-05-07
申请号：US14511215
申请日：2014-10-10
申请人： UNISANTIS ELECTRONICS SINGAPORE PTE LTD.
发明人： FUJIO MASUOKA , NOZOMU HARADA
IPC分类号： H01L29/78 , H01L29/423 , H01L21/324 , H01L29/10 , H01L21/225 , H01L29/66 , H01L29/08
CPC分类号： H01L21/324 , H01L21/2251 , H01L21/2257 , H01L21/28531 , H01L21/31111 , H01L21/31144 , H01L21/8221 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823885 , H01L23/5226 , H01L23/53271 , H01L27/0688 , H01L27/092 , H01L27/11582 , H01L29/0847 , H01L29/41741 , H01L29/42392 , H01L29/66666 , H01L29/78618 , H01L29/78642 , H01L29/78696 , H01L29/788 , H01L29/792
摘要： A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上的半导体柱中形成SGT并形成布线半导体层，以便与存在于半导体柱的中心部分的杂质区域的侧表面或栅极导体层。形成在布线半导体层的侧面的第一合金层直接连接到杂质区域和栅极导体层，并且通过形成在形成的第二合金层的上表面上的接触孔与输出布线金属层连接在布线半导体层的上表面和侧面。

70. 发明申请

US20140183650A1 CMOS CIRCUIT AND METHOD FOR FABRICATING THE SAME 有权
标题翻译： CMOS电路及其制造方法
公开(公告)号：US20140183650A1
公开(公告)日：2014-07-03
申请号：US13845184
申请日：2013-03-18
申请人： SK HYNIX INC.
发明人： Kyong-Bong ROUH , Shang-Koon NA , Mi-Ri LEE , Hun-Sung LEE
IPC分类号： H01L29/49
CPC分类号： H01L21/823814 , H01L21/02532 , H01L21/02592 , H01L21/2251 , H01L21/28035 , H01L21/324 , H01L21/8238 , H01L21/823828 , H01L21/823842
摘要： A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.
摘要翻译：半导体器件包括形成在半导体衬底上的半导体衬底和栅极绝缘层。在栅绝缘层上形成栅电极。栅电极包括含有掺杂剂的含硅电极，捕获掺杂剂的捕获材料以及控制掺杂剂活化的活化控制材料。

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