专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20170025180A1 CONTROLLER FOR BIASING SWITCHING ELEMENT OF A PAGE BUFFER OF A NON VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的页面缓冲器的偏移切换元件的控制器
公开(公告)号：US20170025180A1
公开(公告)日：2017-01-26
申请号：US15214161
申请日：2016-07-19
申请人： SK hynix Inc.
发明人： Alessandro SANASI
IPC分类号： G11C16/26 , G11C16/04 , G11C16/08 , G11C16/10 , G11C29/42
CPC分类号： G11C16/26 , G11C7/04 , G11C7/1078 , G11C7/12 , G11C8/06 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/3418 , G11C29/028 , G11C29/42 , G11C2029/0403 , G11C2029/0411
摘要： Disclosed herein is a controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, comprising: a look-up table configured to store a plurality of address zones: and a matching logic configured to match one address zone among the plurality of address zones based on all inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.
摘要翻译：本文公开了一种用于非易失性存储器件的控制块，其包括将位线耦合到相应的页缓冲器的开关元件，包括：查找表，其被配置为存储多个地址区：以及配置为基于所有输入的行地址来匹配多个地址区中的一个地址区，并且基于地址区产生用于读取非易失性存储器的操作的开关元件的偏置电压，其中多个地址区被定义通过对具有不同于前缀值的当前值而不同的具有IV特性的字线进行分组。

62. 发明申请

US20170018296A1 SEMICONDUCTOR MEMORY DEVICE OUTPUTTING READ-BUSY SIGNAL AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体存储器件输出包括其中的READ-BUSY信号和存储器系统
公开(公告)号：US20170018296A1
公开(公告)日：2017-01-19
申请号：US14967621
申请日：2015-12-14
申请人： SK hynix Inc.
发明人： Jae Hyeong JEONG , Kwang Hyun KIM
IPC分类号： G11C8/06 , G11C7/10 , G11C7/22
CPC分类号： G11C8/06 , G11C7/1045 , G11C7/1063 , G11C7/109 , G11C7/22
摘要： A semiconductor memory device includes a plurality of memory cells; a peripheral circuit suitable for controlling the memory cells, and operating in first and second modes respectively corresponding to enablement and disablement of a chip selection signal; and a ready-busy signal generator suitable for biasing a ready-busy line according to whether the peripheral circuit is in a ready or busy state during the enablement of the chip selection signal. Communication between the semiconductor memory device and an external device is allowed in the first mode. The communication between the semiconductor memory device and the external device is not allowed in the second mode.
摘要翻译：半导体存储器件包括多个存储单元; 适用于控制存储器单元的外围电路，并分别对应于芯片选择信号的使能和禁止工作在第一和第二模式中; 以及一个就绪忙信号发生器，其适合于在芯片选择信号的使能期间根据外围电路是否处于就绪或忙状态来偏置就绪线路。在第一模式中允许半导体存储器件与外部器件之间的通信。在第二模式中，不允许半导体存储器件与外部器件之间的通信。

63. 发明授权

US09542986B2 Low power input gating 有权
标题翻译：低功率输入门控
公开(公告)号：US09542986B2
公开(公告)日：2017-01-10
申请号：US14849902
申请日：2015-09-10
申请人： ARM Limited
发明人： Andy Wangkun Chen , Gus Yeung , Yew Keong Chong
IPC分类号： G11C8/18 , G11C8/06
CPC分类号： G11C8/18 , G11C5/141 , G11C8/06
摘要： Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.
摘要翻译：本文所描述的各种实现涉及用于实现低功率输入门控的集成电路。在一个实现中，集成电路可以包括芯片使能装置，其被配置为接收和使用时钟输入信号，以基于芯片使能信号切换存储器的控制输入。集成电路可以包括被配置为锁存存储器的控制输入的锁存装置。集成电路可以包括耦合在芯片使能装置和锁存装置之间的锁存使能装置。锁存使能装置可以被配置为从芯片使能装置接收时钟输入信号，并且使用时钟输入信号基于锁存使能信号来对锁存器件进行门控，以便有选择地将时钟输入信号切换到控制输入的记忆。

64. 发明授权

US09530474B2 Semiconductor integrated circuit including semiconductor memory apparatus including a plurality of banks 有权
标题翻译：半导体集成电路包括包括多个存储体的半导体存储装置
公开(公告)号：US09530474B2
公开(公告)日：2016-12-27
申请号：US14809897
申请日：2015-07-27
申请人： SK hynix Inc.
发明人： Hee Jin Byun
IPC分类号： G11C7/22 , G11C8/18 , G11C8/04 , G11C8/06 , G11C8/12 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1039 , G11C7/1084 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C8/04 , G11C8/06 , G11C8/12 , G11C8/18
摘要： A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.
摘要翻译：半导体存储装置包括：存储单元区域，包括多个存储体，每个存储体具有对应于第一组的多个八位字节存储体和对应于第二组的多个字节存储体; 以及控制单元，被配置为产生多个控制信号，以将数据信号输入到第一组的任何一个八位字节组和具有预定余量的第二组的任何一个八位字节组。

65. 发明申请

US20160267946A1 STACK MEMORY DEVICE AND METHOD FOR OPERATING SAME 审中-公开
标题翻译：堆叠存储器件及其操作方法
公开(公告)号：US20160267946A1
公开(公告)日：2016-09-15
申请号：US15032935
申请日：2014-10-27
申请人： SILICONFILE TECHNOLOGIES INC.
发明人： Sang Wook Ahn , Huy Chan Jung , Yong Woon Lee , Heui-Gyun Ahn , Do Young Lee
IPC分类号： G11C5/02 , G11C8/06 , G11C8/10 , H01L25/065 , G11C5/06 , H01L23/48
CPC分类号： G11C5/025 , G11C5/063 , G11C8/06 , G11C8/10 , H01L23/48 , H01L23/481 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence.
摘要翻译：本发明提供了一种堆栈存储装置及其操作方法。根据本发明的堆叠存储器件提供有：第一存储器芯片，其中第一类型存储器单元在行方向和列方向上重复布置，并且包括一个或多个单元阵列，其中转储线是连接到每个第一类型存储单元; 以及第二存储器芯片，其中第二类型存储器单元在行方向和列方向上重复排列，并且包括一个或多个单元阵列，其中转储线连接到每个第二类型存储单元，其中第一焊盘被连接到第一类型存储单元的转储线和第二焊盘连接到第二类型存储单元的转储线，第一焊盘和第二焊盘具有一一对应关系。

66. 发明申请

US20160266807A1 METHOD FOR NON-VOLATILE DATA STORAGE AND RETRIEVAL 审中-公开
标题翻译：非易失性数据存储和检索方法
公开(公告)号：US20160266807A1
公开(公告)日：2016-09-15
申请号：US15144653
申请日：2016-05-02
申请人： Xitore, Inc.
发明人： Mike Hossein Amidi , Hossein Hashemi
IPC分类号： G06F3/06 , G11C29/52 , G06F11/10 , G06F12/08 , G06F12/10
CPC分类号： G06F9/30 , G06F3/0605 , G06F3/0619 , G06F3/0635 , G06F3/0655 , G06F3/0659 , G06F3/0661 , G06F3/0673 , G06F3/0679 , G06F11/10 , G06F11/1004 , G06F11/1068 , G06F12/0223 , G06F12/06 , G06F12/0638 , G06F12/0802 , G06F12/0888 , G06F12/10 , G06F2206/1014 , G06F2212/152 , G06F2212/261 , G06F2212/401 , G06F2212/403 , G11C8/06 , G11C29/52 , G11C2029/0411
摘要： A method of storing data is provided. The method includes receiving commands from a system memory controller of a computer system. The commands include logical addresses and are received by a computer memory device comprising a parallel memory interface operatively coupled to the system memory controller and operatively coupled to a non-volatile memory. The method further includes responding to the commands by translating the received logical addresses to corresponding physical addresses of the non-volatile memory, receiving data from the system memory controller by the parallel memory interface, and storing the data at memory locations of the non-volatile memory corresponding to the physical addresses.
摘要翻译：提供了一种存储数据的方法。该方法包括从计算机系统的系统存储器控制器接收命令。这些命令包括逻辑地址并且由计算机存储器件接收，该计算机存储器设备包括可操作地耦合到系统存储器控制器并且可操作地耦合到非易失性存储器的并行存储器接口。该方法还包括通过将接收到的逻辑地址转换为非易失性存储器的相应物理地址来响应命令，通过并行存储器接口从系统存储器控制器接收数据，并将数据存储在非易失性存储器的存储器位置内存对应的物理地址。

67. 发明申请

US20160259723A1 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体器件及其工作方法
公开(公告)号：US20160259723A1
公开(公告)日：2016-09-08
申请号：US14724612
申请日：2015-05-28
申请人： SK hynix Inc. , Industry-University Cooperation Foundation Hanyang University
发明人： Tae-Hwa LEE , Yoon-Jang JOE , Jae-Hyuk CHA
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G06F2212/7201 , G11C8/06 , G11C16/10 , G11C16/26
摘要： A semiconductor device includes a mapping table that stores a corresponding relation between a logical address defined on a basis of regions and a physical address defined on a basis of extents, wherein one or more extents are dynamically allocated to one region.
摘要翻译：半导体器件包括映射表，其存储基于区域定义的逻辑地址和基于范围定义的物理地址之间的对应关系，其中一个或多个范围被动态分配给一个区域。

68. 发明授权

US09436548B2 ECC bypass using low latency CE correction with retry select signal 有权
标题翻译： ECC旁路使用低延迟CE校正与重试选择信号
公开(公告)号：US09436548B2
公开(公告)日：2016-09-06
申请号：US14098561
申请日：2013-12-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Benjiman L. Goodman , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： G11C29/00 , G06F11/10 , G11C29/44 , G11C29/04 , G11C29/42 , G11C8/06
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1012 , G06F11/1048 , G06F11/1052 , G11C8/06 , G11C29/42 , G11C29/44 , G11C2029/0411
摘要： A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
摘要翻译：存储器控制器配备有用于不同复杂度错误水平的多个纠错电路，但是请求的数据最初经由提供最低存储器延迟的旁路路径发送到请求单元（例如，处理器）。请求单元执行错误检测，并且如果发现错误，则将重试选择信号发送到存储器控制器。重试选择信号提供了哪个错误校正单元应该用于提供错误的完整校正的指示，但是添加最小等待时间。在重试传输中，控制器使用由重试选择信号指示的特定纠错单元。存储器控制器还可以具有持续错误检测电路，其在由多个重试选择信号重复指示错误时将地址标识为有缺陷，并且控制逻辑可以使用适当的纠错单元自动发送所请求的数据。

69. 发明授权

US09424902B2 Memory controller and associated method for generating memory address 有权
标题翻译：存储器控制器及相关的生成存储器地址的方法
公开(公告)号：US09424902B2
公开(公告)日：2016-08-23
申请号：US14228390
申请日：2014-03-28
申请人： MStar Semiconductor, Inc.
发明人： Chung-Ching Chen , Chen-Nan Lin , Yung Chang
IPC分类号： G06F12/00 , G11C8/18 , G11C8/06 , G11C8/10
CPC分类号： G11C8/18 , G11C8/06 , G11C8/10
摘要： A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address.
摘要翻译：存储器控制器连接到双数据速率动态随机存取存储器（DDR DRAM）和存取单元。所述存储器控制器包括：处理单元，被配置为接收由所述访问单元生成的系统地址; 以及位于所述处理单元中的映射单元，被配置为将所述系统地址转换为存储器地址并将所述存储器地址发送到所述DDR DRAM。当DDR DRAM的突发长度为L且L = 2x（其中L和x为正整数）时，来自最低有效位（LSB）的存储器地址的第（x + 1）位包括在存储体组地址的内存地址。

70. 发明授权

US09324397B1 Common die for supporting different external memory types with minimal packaging complexity 有权
标题翻译：用于支持不同外部存储器类型的通用裸片，具有最小的封装复杂性
公开(公告)号：US09324397B1
公开(公告)日：2016-04-26
申请号：US14598528
申请日：2015-01-16
申请人： QUALCOMM Incorporated
发明人： Kunal Mukesh Desai , Piyush Gupta , Bernie Jord Yang , Umesh Madhusudan Rao
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10 , G11C8/06 , G11C8/18
CPC分类号： G11C7/22 , G06F13/1694 , G11C7/10 , G11C8/06 , G11C8/18 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.
摘要翻译：一种可配置管芯，包括被配置为传送控制和地址（CA）信号和数据（DQ））信号的逻辑元件，以及与逻辑元件通信的第一通用物理接口（PHY）和第二通用PHY，其中每个第一通用PHY和第二通用PHY可配置为CA PHY和DQ PHY，并且其中逻辑元件可配置为将CA信号和DQ信号传送到第一和第二通用PHY中的不同PHY。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式