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61. 发明授权

US09484083B2 Semiconductor device and semiconductor storage device 有权
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US09484083B2
公开(公告)日：2016-11-01
申请号：US14611970
申请日：2015-02-02
申请人： Socionext, Inc.
发明人： Shinichi Moriwaki
IPC分类号： G11C8/08 , G11C11/417 , G11C5/02 , G11C5/14
CPC分类号： G11C11/417 , G11C5/02 , G11C5/148 , G11C8/08
摘要： A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line.
摘要翻译：半导体器件包括可在选择和非选择之间切换的电路块，以及设置在电路块和第一电源线之间的漏电流控制电路。泄漏电流控制电路包括设置在电路块和第一电源线之间的第一晶体管，以及设置在电路块和第一电源线之间的电阻器件。

62. 发明授权

US09466342B2 Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof 有权
标题翻译：具有用于控制漏电流的源极和字线电压调节电路的晶体管及其方法
公开(公告)号：US09466342B2
公开(公告)日：2016-10-11
申请号：US14593395
申请日：2015-01-09
申请人： Kabushiki Kaisha Toshiba
发明人： Shinji Miyano
IPC分类号： G11C11/00 , G11C7/10 , G11C5/14 , G11C11/4074 , G11C11/4091 , G11C11/417 , G11C8/08 , G11C11/418
CPC分类号： G11C7/10 , G11C5/14 , G11C5/147 , G11C5/148 , G11C7/1096 , G11C8/08 , G11C11/4074 , G11C11/4091 , G11C11/417 , G11C11/418
摘要： According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors.
摘要翻译：根据一个实施例，半导体存储器件包括源极电压调节电路和字线电压调整电路，其被配置为响应于模式而分别提供具有电压调整的电压的源极电压供给端和字线用于在保持状态模式和活动状态模式之间切换的切换信号，其中源电压供给端连接到形成存储单元的触发器的MOS晶体管的源极，并且字线连接到存取晶体管的栅极。

63. 发明授权

US09443601B2 Holdup capacitor energy harvesting 有权
标题翻译：夹持电容器能量收集
公开(公告)号：US09443601B2
公开(公告)日：2016-09-13
申请号：US14479559
申请日：2014-09-08
申请人： SanDisk Enterprise IP LLC
发明人： Gregg S. Lucas , Robert W. Ellis
IPC分类号： G11C16/04 , G11C16/30 , G06F1/30 , G06F11/14 , G11C5/14 , G11C16/22
CPC分类号： G11C16/30 , G06F1/30 , G06F11/14 , G11C5/148 , G11C16/225
摘要： The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes performing a power fail operation on a first section of the storage device. The power fail operation includes supplying power, via an energy storage device, to the first section of the storage device, where the energy storage device is distinct from a power source used during normal operation of the storage device, and where supplying power via the energy storage device includes switching the output of the energy storage device from an output of a boost regulator to an input of the boost regulator. The power fail operation also includes performing data hardening on the first section of the storage device.
摘要翻译：这里描述的各种实施例包括用于保护存储设备中的数据的电路，方法和/或设备。一方面，一种方法包括在存储装置的第一部分上执行电源故障操作。电源故障操作包括通过能量存储设备向存储设备的第一部分供电，其中能量存储设备不同于在存储设备的正常操作期间使用的电源，并且通过能量供应电力存储装置包括将能量存储装置的输出从升压调节器的输出切换到升压调节器的输入。电源故障操作还包括在存储设备的第一部分上执行数据硬化。

64. 发明申请

US20160252938A1 DEVICE AND MEMORY CONTROL METHOD 审中-公开
标题翻译：设备和存储器控制方法
公开(公告)号：US20160252938A1
公开(公告)日：2016-09-01
申请号：US15016637
申请日：2016-02-05
申请人： FUJITSU LIMITED
发明人： Kazuaki OISHI
IPC分类号： G06F1/26 , G11C5/14 , G06F3/06 , G11C14/00
CPC分类号： G11C5/148 , G06F1/3225 , G06F1/3275 , G11C11/005 , G11C14/0063 , G11C16/225 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A device includes: a nonvolatile memory configured to store data; a volatile memory configured to store the data read out from the nonvolatile memory; a processor configured to perform processing using the data stored in the volatile memory; and a measurement circuit configured to measure standby power of the volatile memory when the power of the volatile memory is turned on, wherein the processor is configured to control, based on a measurement result outputted from the measurement circuit, power supply to the volatile memory while the processor is to be intermittently operated.
摘要翻译：一种设备包括：被配置为存储数据的非易失性存储器; 易失性存储器，被配置为存储从非易失性存储器读出的数据; 处理器，被配置为使用存储在所述易失性存储器中的数据来执行处理; 以及测量电路，其被配置为当所述易失性存储器的电源接通时测量所述易失性存储器的待机功率，其中所述处理器被配置为基于从所述测量电路输出的测量结果来控制向所述易失性存储器的电力供应，处理器将被间歇地操作。

65. 发明授权

US09412461B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09412461B1
公开(公告)日：2016-08-09
申请号：US14846106
申请日：2015-09-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuyo Kodama
IPC分类号： G11C11/4074 , G11C11/4094 , G11C7/08 , G11C7/12 , G11C7/06 , G11C5/14 , G11C16/26 , G11C16/10 , G11C16/30 , G11C16/24
CPC分类号： G11C16/26 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/06 , G11C7/08 , G11C7/12 , G11C11/4074 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/30
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first memory cell transistor; a first bit line; a first sense amplifier unit; a voltage generator; and a switch circuit. In a case where a power-supply voltage is equal to or lower than a first voltage and is higher than a second voltage when an access operation to the first memory cell transistor is started, the first sense amplifier unit is electrically disconnected from the first bit line and is electrically connected to the voltage generator via the switch circuit.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：第一存储单元晶体管; 第一个位线第一感测放大器单元; 电压发生器; 和开关电路。在第一存储单元晶体管的访问操作开始时，在电源电压等于或低于第一电压并且高于第二电压的情况下，第一读出放大器单元与第一位电并且经由开关电路电连接到电压发生器。

66. 发明申请

US20160218716A1 Power Sequencing For Embedded Flash Memory Devices 有权
公开(公告)号：US20160218716A1
公开(公告)日：2016-07-28
申请号：US15088038
申请日：2016-03-31
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Thuan Vu , Anh Ly , Hung Quoc Nguyen
IPC分类号： H03K19/0185 , G11C16/30
CPC分类号： G06F1/266 , G06F1/28 , G11C5/14 , G11C5/143 , G11C5/147 , G11C5/148 , G11C7/20 , G11C11/4074 , G11C16/30 , H03K19/018521
摘要： A system and method for improved power sequencing within an embedded flash memory device is disclosed.

67. 发明授权

US09390789B2 Semiconductor storage device having an SRAM memory cell and control and precharge circuits 有权
标题翻译：具有SRAM存储单元和控制和预充电电路的半导体存储器件
公开(公告)号：US09390789B2
公开(公告)日：2016-07-12
申请号：US14942861
申请日：2015-11-16
申请人： Renesas Electronics Corporation
发明人： Yuichiro Ishii
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C5/148 , G11C7/12 , G11C2207/2227
摘要： A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
摘要翻译：半导体存储装置包括由驱动晶体管，转移晶体管和负载晶体管组成的SRAM存储单元，连接到与存储单元连接的位线的I / O电路，以及操作模式控制电路，在恢复待机模式和正常操作模式之间的I / O电路的模式，其中I / O电路包括将数据写入位线的写入驱动器，从位线读取数据的读出放大器，插入的第一开关在位线和写入驱动器之间，插入在位线和读出放大器之间的第二开关，预充电位线的预充电电路，以及根据信号控制第一和第二开关和预充电电路的控制电路从操作模式控制电路。

68. 发明申请

US20160189767A1 SEMICONDUCTOR DEVICES AND INTEGRATED CIRCUITS INCLUDING THE SAME 有权
公开(公告)号：US20160189767A1
公开(公告)日：2016-06-30
申请号：US15060984
申请日：2016-03-04
申请人： SK hynix Inc.
发明人： Sang Il PARK
IPC分类号： G11C11/406 , G11C11/4091 , G11C11/4074 , G11C11/4093
CPC分类号： G11C11/40615 , G11C5/148 , G11C11/4074 , G11C11/4091 , G11C11/4093 , G11C11/4094
摘要： A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals.

69. 发明申请

US20160180892A1 SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP 有权
公开(公告)号：US20160180892A1
公开(公告)日：2016-06-23
申请号：US15058009
申请日：2016-03-01
申请人： Micron Technology, Inc.
发明人： Ted Pekny , Jeff Yu
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G06F1/3275 , G11C5/14 , G11C5/148 , G11C7/20
摘要： Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory.

70. 发明授权

US09355723B1 Semiconductor device including a non-volatile memory preserving data stored in a volatile memory when powered off 有权
标题翻译：半导体装置包括非易失性存储器，用于在关闭电源时保存存储在易失性存储器中的数据
公开(公告)号：US09355723B1
公开(公告)日：2016-05-31
申请号：US14732037
申请日：2015-06-05
申请人： SK hynix Inc.
发明人： Sangkug Lym
IPC分类号： G11C11/00 , G11C14/00
CPC分类号： G11C14/00 , G11C5/143 , G11C5/148 , G11C7/20 , G11C11/005 , G11C16/225 , G11C16/30
摘要： A semiconductor device may include a controller configured to generate a data retention path control signal in response to a power condition change signal. The semiconductor device may include a plurality of data retention paths configured to sequentially couple a plurality of global input/output (I/O) lines coupled to a volatile memory to a dummy I/O line in response to the data retention path control signal. The semiconductor device may include a dummy I/O pad coupled to the dummy I/O line. The semiconductor device may include a non-volatile memory device coupled to the dummy I/O pad, configured to retain a plurality of storage data received from the volatile memory when the volatile memory is powered off, or provide data retained in the volatile memory as recovery data when power is recovered by the volatile memory.
摘要翻译：半导体器件可以包括被配置为响应于电力状况改变信号产生数据保持路径控制信号的控制器。半导体器件可以包括多个数据保持路径，其被配置为响应于数据保持路径控制信号将耦合到易失性存储器的多个全局输入/输出（I / O）线顺序耦合到虚拟I / O线。半导体器件可以包括耦合到虚拟I / O线的虚拟I / O焊盘。半导体器件可以包括耦合到虚拟I / O焊盘的非易失性存储器件，其被配置为当易失性存储器断电时保持从易失性存储器接收的多个存储数据，或者将保留在易失性存储器中的数据提供为当易失性存储器恢复供电时的恢复数据。

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