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61. 发明授权

US4814756A Video display control system having improved storage of alphanumeric and graphic display data 失效
标题翻译：视频显示控制系统改进了字母数字和图形显示数据的存储
公开(公告)号：US4814756A
公开(公告)日：1989-03-21
申请号：US9578
申请日：1987-01-28
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F5/10 , G06F5/12 , G06F5/14 , G09G5/34 , G09G5/40 , H04N7/025 , H04N7/035 , G09G1/16
CPC分类号： G06F5/14 , G06F5/12 , G09G5/343 , G09G5/40 , H04N7/0255 , H04N7/035 , G06F2205/123
摘要： A system for displaying alphanumeric and graphic information on a raster scanned display device, for example, in a teletext system, includes a memory which is updated to change the display. Dynamic changes in the displayed image are provided by assigning a base address to each of one or more zones in the memory and altering the base addresses as required under local or remote control. Alphanumeric and graphic data may be combined on a single displayed page by means of identification data associated with each row or line of data to be displayed. The required capacity of the memory associated with the display device is substantially reduced by assigning a control code to data which is to be repetitively displayed, for example, spaces at the end of a line or fields of uniform color. Selected elements are thus displayed a predetermined number of times without the need for a corresponding number of memory locations. Incoming data may be sotred in a buffer memory at a greater rate than can be processed by the present system by means of a control circuit which inhibits the inputting of data for a period of time when there is a risk of overwriting or erasure of previously stored data.
摘要翻译：用于在例如图文电视系统中的光栅扫描显示设备上显示字母数字和图形信息的系统包括更新以改变显示的存储器。通过为存储器中的一个或多个区域中的每一个分配基地址并且在本地或远程控制下根据需要改变基地址来提供所显示图像的动态变化。字母数字和图形数据可以通过与要显示的每行或数据行相关联的标识数据组合在单个显示页面上。通过将控制代码分配给要重复显示的数据（例如在一行或多个均匀颜色的场的空格）来显着减少与显示设备相关联的存储器的所需容量。所选择的元件因此显示预定次数，而不需要相应数量的存储器位置。输入数据可以以比当前系统可以通过控制电路更大的速率被存储在缓冲存储器中，该控制电路在存在重写或擦除先前存储的风险的一段时间内禁止输入数据数据。

62. 发明授权

US4692894A Overflow/Underflow detection for elastic buffer 失效
标题翻译：弹性缓冲液溢出/下溢检测
公开(公告)号：US4692894A
公开(公告)日：1987-09-08
申请号：US683434
申请日：1984-12-18
申请人： Gerald L. Bemis
发明人： Gerald L. Bemis
IPC分类号： H04L13/08 , G06F5/10 , G06F5/12 , G06F5/14 , H04J3/06 , H04L7/00 , G06F13/00 , H04J3/00
CPC分类号： G06F5/14 , G06F5/12 , H04L25/05 , G06F2205/123
摘要： An elastic buffer includes a memory array for storing received data, each location within the array having an associated cell storing a flag indicative of the most-recently performed (i.e., read or write) on the associated memory location. A potential write overflow of the memory is detected whenever a write attampt is made to a location whose flag indicates a write was most-recently performed. A potential read underflow is detected whenever a read attempt is made to a location when the flag associated with the location next to be read indicates a read was most recently performed. Also, a potential write operation of a memory location prior to the completion of a read on the next location within the array are also generates an overflow/underflow condition. Metastable logic state conditions within the array are avoided because the potential overflow/underflow conditions take cognizance of the finite propogation and setting times of signals within the array. The overflow/underflow signals generated within the array are provided to circuitry which controls the issuance of the underflow/overflow signal by the array. This circuitry includes a circuit which provides an extended time window to allow full decay or setting of any metastable signal applied thereto. The control circuitry ensures that an overflow/underflow detection signal issues only when data is in transit through the buffer.
摘要翻译：弹性缓冲器包括用于存储接收到的数据的存储器阵列，阵列内的每个位置具有相关联的单元，存储指示在相关联的存储器位置上最近执行（即，读或写）的标志。每当对其标志指示写入最近被执行的位置进行写入时，检测到存储器的潜在写入溢出。当与待读取的位置相关联的标志指示读取最近被执行时，每当对某个位置进行读取尝试时，检测到潜在读取下溢。此外，在完成对阵列内的下一个位置的读取之前的存储器位置的潜在写入操作也产生溢出/下溢条件。避免了阵列内的平滑逻辑状态条件，因为潜在的溢出/下溢条件考虑了阵列内信号的有限传播和设定时间。在阵列内产生的溢出/下溢信号被提供给控制阵列发出下溢/溢出信号的电路。该电路包括提供延长的时间窗口以允许对其施加的任何亚稳信号进行完全衰减或设置的电路。控制电路确保仅当数据通过缓冲器传输时才会发生溢出/下溢检测信号。

63. 发明授权

US4525849A Data transmission facility between two asynchronously controlled data processing systems with a buffer memory 失效
标题翻译：两个异步控制数据处理系统之间的数据传输设备与缓冲存储器
公开(公告)号：US4525849A
公开(公告)日：1985-06-25
申请号：US477980
申请日：1983-03-23
申请人： Gerhard Wolf
发明人： Gerhard Wolf
IPC分类号： H04L29/00 , G06F1/12 , G06F5/10 , G06F5/12 , G06F13/00 , H04L13/08 , H04L25/30 , H04L7/00
CPC分类号： G06F5/12 , G06F2205/123
摘要： In order to avoid unambiguous logic switching statuses in a data and control path upon transfer from one clock system of an outputting data processing system into an independent, asynchronous clock system of an accepting data processing system, and wherein a continuous data flow is to be guaranteed at the output of a buffer memory, a control signal indicating the presence of an intermediately stored data word is synchronized into a forwarding timing pattern of the accepting system via a synchronization circuit for forwarding data words from the buffer memory. A forwarding sync control signal is generated by the synchronization circuit. For controlling the in-flow into the buffer memory, a control signal dependent on the forwarding timing pattern of the accepting system is synchronized into the timing pattern of the outputting system over a further synchronization circuit. A request sync control signal is generated which respectively leads to the transfer of a data word together with a strobe signal to the buffer memory which undertakes the intermediate storage on the basis of the strobe signal. In order to guarantee a continuous data flow at the output of the buffer memory, the buffer memory has at least three, and preferably four memory sections.
摘要翻译：为了避免从输出数据处理系统的一个时钟系统转移到接受数据处理系统的独立的异步时钟系统中的数据和控制路径中的明确的逻辑切换状态，并且其中将保证连续的数据流在缓冲存储器的输出端，指示中断存储的数据字的存在的控制信号通过用于从缓冲存储器转发数据字的同步电路被同步到接受系统的转发定时模式。由同步电路产生转发同步控制信号。为了控制进入缓冲存储器的流入，取决于接受系统的转发定时模式的控制信号通过另一同步电路被同步到输出系统的定时模式。生成请求同步控制信号，分别导致数据字与选通信号一起传送到基于选通信号进行中间存储的缓冲存储器。为了保证缓冲存储器输出端的连续数据流，缓冲存储器具有至少三个，最好是四个存储器部分。

64. 发明授权

US4439786A Apparatus and method for processing television picture signals and other information 失效
标题翻译：用于处理电视图像信号和其他信息的装置和方法
公开(公告)号：US4439786A
公开(公告)日：1984-03-27
申请号：US320058
申请日：1981-11-10
申请人： Gyongyver Claydon , Gordon D. Iles
发明人： Gyongyver Claydon , Gordon D. Iles
IPC分类号： G06F5/10 , G06F5/12 , H04N5/073 , H04N5/04
CPC分类号： G06F5/12 , H04N5/0736 , G06F2205/123
摘要： A problem arises when simultaneous attempts are made to write and read from the same location in a random access memory. The invention deals with this problem by delaying the writing operations automatically by a varying amount to prevent attempts at simultaneous writing and reading: and preferably to position each write operation approximately mid-way between two read operations.The invention is particularly applicable to a television synchronizer. In a television synchronizer video information is digitized and then fed into a memory by write clock signals derived from the video information, e.g. from its line synchronizing pulses. It is fed out of the memory by read clock signals derived from some other source.The invention is also applicable to standards conversion systems, noise reduction systems and picture size reduction and expansion systems.
摘要翻译：当同时尝试从随机存取存储器中的相同位置进行写入和读取时，会出现问题。本发明通过将写入操作自动地延迟一个变化量来处理这个问题，以防止同时写入和读取的尝试：并且优选地将每个写入操作大致中间地定位在两个读取操作之间。本发明特别适用于电视同步器。在电视同步器中，视频信息被数字化，然后通过从视频信息导出的写时钟信号，例如，从其行同步脉冲。它通过从其他来源得到的读取时钟信号从存储器中送出。本发明也适用于标准转换系统，降噪系统和图像尺寸缩小和扩展系统。

65. 发明授权

US3012230A Computer format control buffer 失效
标题翻译：计算机格式控制缓冲区
公开(公告)号：US3012230A
公开(公告)日：1961-12-05
申请号：US68694657
申请日：1957-09-30
申请人： ELECTRONIC ENG CO
发明人： GALAS THEODORE A , SUBLETT CHARLES R
IPC分类号： G06F5/10 , G06F5/12 , G11B20/12
CPC分类号： G06F5/12 , G06F2205/123 , G11B20/1205

66. 发明授权

US10496368B1 Systems and methods for memory FIFO control 有权
公开(公告)号：US10496368B1
公开(公告)日：2019-12-03
申请号：US16055968
申请日：2018-08-06
申请人： Micron Technology, Inc.
发明人： Andrew W. Skreen
IPC分类号： G06F12/02 , G06F5/12 , G06F13/42 , G06F12/00
CPC分类号： G06F5/12 , G06F12/023 , G06F13/4234 , G06F12/00 , G06F12/02
摘要： The present disclosure relates generally to improved systems and methods for control of a first-in, first-out (FIFO memory). More specifically, the present disclosure relates to improved timing and/or control signals used to control operation of the FIFO memory. For example, access circuitry of the memory device may pulse a control signal used to control latching of data at the FIFO memory. Further, the access circuitry may pulse one or more bits of a column address bus to generate a column address corresponding to data to be latched at the FIFO memory. Accordingly, the current, power, and/or area consumed by the memory device may be reduced.

67. 发明申请

US20190235927A1 DATA SYNCHRONIZATION FOR IMAGE AND VISION PROCESSING BLOCKS USING PATTERN ADAPTERS 审中-公开
公开(公告)号：US20190235927A1
公开(公告)日：2019-08-01
申请号：US16377966
申请日：2019-04-08
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Hetul Sanghvi , Mihir Narendra Mody
IPC分类号： G06F9/50 , G06F9/52 , G06F9/48 , G06F11/07
CPC分类号： G06F9/5044 , G06F5/12 , G06F9/4881 , G06F9/4887 , G06F9/52 , G06F9/522 , G06F9/544 , G06F11/0757 , G06T1/20
摘要： A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

68. 发明申请

US20190004963A1 DUAL POINTER FOR MEMORY MAPPED INTERFACE COMMUNICATION 审中-公开
公开(公告)号：US20190004963A1
公开(公告)日：2019-01-03
申请号：US15992725
申请日：2018-05-30
申请人： Intel Corporation
发明人： Anant Raj Gupta , Ingo Volkening , Jun Ye Zhou
IPC分类号： G06F12/10 , G06F13/16
CPC分类号： G06F12/10 , G06F3/0656 , G06F5/12 , G06F13/1673 , G06F13/4282 , G06F2212/1008 , G06F2213/0026
摘要： A set of data entries is transferred via a memory mapped interface from an external peripheral device to a processor device and is stored in a shared memory region. Based on a first pointer to the shared memory region, a first process executed by the processor device processes a first group of the data entries. Based on a second pointer to the shared memory region, a second process executed by the processor device processes a second group of the data entries. The second process indicates the second pointer to the first process. The first process indicates a lower one of the first pointer and the second pointer to the peripheral device.

69. 发明申请

US20180107611A1 ADJUSTMENTS OF BUFFER CREDITS FOR OPTIMIZING THE NUMBER OF RETRY OPERATIONS AND TRANSFER READY OPERATIONS 审中-公开
公开(公告)号：US20180107611A1
公开(公告)日：2018-04-19
申请号：US15842414
申请日：2017-12-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Roger G. Hathorn , Bret W. Holley , Matthew J. Kalos
IPC分类号： G06F13/12 , H04L12/801 , G06F13/36 , G06F3/06 , G06F13/40 , G06F13/16 , G06F5/12
CPC分类号： G06F13/126 , G06F3/0613 , G06F3/0656 , G06F3/067 , G06F5/12 , G06F13/1642 , G06F13/1673 , G06F13/36 , G06F13/4027 , G06F2003/0691 , G06F2205/126 , G06F2213/0008 , H04L47/39
摘要： A control unit monitors a number of transfer ready operations and a number of retry operations during a monitoring period during communication with a plurality of channels. Based, on the monitoring, a number of buffer credits for communication with the plurality of channels is adjusted.

70. 发明授权

US09860654B2 Method for synchronizing the reproduction of a digital signal sent by a transmitter to a plurality of mobile audio terminals 有权
公开(公告)号：US09860654B2
公开(公告)日：2018-01-02
申请号：US15137392
申请日：2016-04-25
申请人： SIVANTOS PTE. LTD.
发明人： Jie Zhang , Mattias Lampe
IPC分类号： H04R25/00 , H04R27/00 , H04J3/06 , H04W28/02 , G06F5/12 , H04L7/00 , H04L25/02
CPC分类号： H04R25/505 , G06F5/12 , H04J3/0632 , H04L7/0029 , H04L25/0262 , H04R25/55 , H04R25/552 , H04R25/554 , H04R25/558 , H04R27/00 , H04R2225/43 , H04R2225/55 , H04R2420/07 , H04W28/0278
摘要： A method for synchronizing the reproduction of a digital signal sent by a transmitter to a plurality of mobile audio terminals. The transmitter sends the digital signal as a multiplicity of data packets at a data rate that is constant as an average over time. A signal receiver of each mobile audio terminal receives at least a subset of the multiplicity of data packets and generates a time reference signal. A FIFO signal with information on an occupancy level of a FIFO memory of the mobile audio terminal at specific time points is generated, an instantaneous reproduction speed is set on the basis of the time reference signal and the FIFO signal, the audio reproduction unit reproduces at the instantaneous reproduction speed samples corresponding to the digital signal. The occupancy level of the FIFO memory is thereby kept constant as an average over time.

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