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61. 发明授权

US06782463B2 Shared memory array 失效
标题翻译：共享内存数组
公开(公告)号：US06782463B2
公开(公告)日：2004-08-24
申请号：US09953751
申请日：2001-09-14
申请人： Mark A. Schmisseur , Jeff McCoskey , Timothy J. Jehl
发明人： Mark A. Schmisseur , Jeff McCoskey , Timothy J. Jehl
IPC分类号： G06F1200
CPC分类号： G06F15/7846 , G06F12/0802 , G06F2212/2515
摘要： Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.
摘要翻译：公开了一种设备，其包括耦合到单个存储器阵列的核心处理电路，其被划分为至少第一部分作为核心处理电路的高速缓存存储器，以及第二部分作为可由一个或多个数据传输设备访问的存储器通过独立于核心处理电路的数据总线。

62. 发明授权

US06606686B1 Unified memory system architecture including cache and directly addressable static random access memory 有权
标题翻译：统一的内存系统架构，包括缓存和直接可寻址的静态随机存取存储器
公开(公告)号：US06606686B1
公开(公告)日：2003-08-12
申请号：US09603645
申请日：2000-06-26
申请人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
发明人： Sanjive Agarwala , Charles L. Fuoco , David A. Comisky , Timothy D. Anderson , Christopher L. Mobley
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0864 , G06F2212/2515 , G06F2212/601
摘要： A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of ways as directly addressable memory and configuring remaining ways as cache memory. Control logic inhibits indication that tag bits matches address bits and that a cache entry is the least recently used for cache eviction if the corresponding way is configured as directly addressable memory. In an alternative embodiment, the memory is selectively configurable as cache memory and directly addressable memory by configuring a selected number of sets equal to 2M, where M is an integer, as cache memory and configuring remaining sets as directly addressable memory.
摘要翻译：数据处理装置包括中央处理单元和可配置为高速缓冲存储器和可直接寻址存储器的存储器。存储器可选择性地配置为高速缓冲存储器和可直接寻址的存储器，通过将选定数量的方式配置为直接可寻址存储器并且将剩余方式配置为高速缓冲存储器。控制逻辑禁止标签位匹配地址位的指示，并且如果相应的方式被配置为直接可寻址存储器，则高速缓存条目是最近最少用于高速缓存驱逐的指示。在替代实施例中，通过将等于2M的选定数量的集合（其中M是整数）配置为高速缓冲存储器并将剩余集合配置为直接可寻址存储器，可选地将存储器配置为高速缓存存储器和直接寻址存储器。

63. 发明授权

US06606684B1 Multi-tiered memory bank having different data buffer sizes with a programmable bank select 有权
标题翻译：具有不同数据缓冲区大小的多层存储体，具有可编程存储区选择
公开(公告)号：US06606684B1
公开(公告)日：2003-08-12
申请号：US09541114
申请日：2000-03-31
申请人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
发明人： Hebbalalu S. Ramagopal , Michael Allen , Jose Fridman , Marc Hoffman
IPC分类号： G06F1210
CPC分类号： G06F12/0802 , G06F12/0846 , G06F2212/2515
摘要： An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
摘要翻译：公开了一种具有核心处理器和多个高速缓冲存储器组的装置。高速缓冲存储器组以这样的方式连接到核心处理器，以便为所述核心处理器提供基本同时的数据访问。

64. 发明申请

US20030088738A1 Method for using a portion of the system cache as a trace array 有权
标题翻译：将系统高速缓存的一部分用作跟踪数组的方法
公开(公告)号：US20030088738A1
公开(公告)日：2003-05-08
申请号：US10003857
申请日：2001-11-02
发明人： David B. Fox , Joseph M. Hoke , Tin-Chee Lo
IPC分类号： G06F012/00
CPC分类号： G06F11/3636 , G06F11/348 , G06F12/0802 , G06F2201/885 , G06F2212/2515
摘要： A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.
摘要翻译：公开了一种用于指示计算系统从原始高速缓冲存储器分配跟踪阵列的方法，其中该方法包括将原始高速缓存存储器分为缩小大小的高速缓冲存储器和跟踪阵列，允许将跟踪信号数据存储到跟踪中阵列，并允许从跟踪数组中检索跟踪信号数据。

65. 发明授权

US06400599B1 Cache memory cell with a pre-programmed state 有权
标题翻译：具有预编程状态的高速缓存存储单元
公开(公告)号：US06400599B1
公开(公告)日：2002-06-04
申请号：US09569543
申请日：2000-05-12
申请人： Peter H. Voss
发明人： Peter H. Voss
IPC分类号： G11C1100
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data read into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.
摘要翻译：包括第一组存储器单元的存储器件，具有预编程状态的第二组存储器单元，以及被配置为访问包括在存储器单元的第一段中的数据的电路。当从第二组存储器单元读取数据时，该电路包括使能信号，以确定由第二组存储器单元输出的数据是否是在正常操作期间存储的预编程数据或数据。对于一个实施例，在第一组存储器单元和第二组存储器单元之间以一致的方式执行从存储器单元读取或从其中检索的数据。

66. 发明授权

US06282644B1 Apparatus and method for storing BIOS data of computer system 失效
标题翻译：用于存储计算机系统的BIOS数据的装置和方法
公开(公告)号：US06282644B1
公开(公告)日：2001-08-28
申请号：US09227159
申请日：1999-01-08
申请人： Jin-Suk Ko
发明人： Jin-Suk Ko
IPC分类号： G06F9445
CPC分类号： G06F12/0802 , G06F9/4403 , G06F2212/2515
摘要： An apparatus and a method for storing a BIOS data of a computer system are disclosed. The apparatus includes a first storing apparatus for performing a function as a memory and a function as a storing apparatus for storing a BIOS data therein, a second storing apparatus in which a BIOS data stored in the first storing apparatus is copied and stored therein, a CPU(Central Processing Unit) for accessing a BIOS data stored in the first storing apparatus and driving a computer system when an electric power is supplied to the computer system, a main power controlling for supplying or blocking a main power, a controller for controlling each element of the system, and a system power unit for applying a system power to the first storing apparatus and the controller, respectively, for thereby significantly decreasing the fabrication cost of the system by storing a BIOS data into a SDRAM used as a cache memory of the computer system.
摘要翻译：公开了一种用于存储计算机系统的BIOS数据的装置和方法。该装置包括用于执行作为存储器的功能的第一存储装置和用于存储其中的BIOS数据的存储装置的功能;第二存储装置，其中存储在第一存储装置中的BIOS数据被复制和存储在其中，第二存储装置 CPU（中央处理单元），用于访问存储在第一存储装置中的BIOS数据，并且当向计算机系统提供电力时驱动计算机系统;主电源控制，用于提供或阻塞主电源;控制器，用于控制每个系统功率单元和用于将系统功率分别施加到第一存储装置和控制器的系统功率单元，从而通过将BIOS数据存储到用作高速缓冲存储器的高速缓冲存储器的SDRAM中来显着降低系统的制造成本计算机系统。

67. 发明授权

US06070229A Cache memory cell with a pre-programmed state 失效
标题翻译：具有预编程状态的高速缓存存储单元
公开(公告)号：US06070229A
公开(公告)日：2000-05-30
申请号：US982822
申请日：1997-12-02
申请人： Peter H. Voss
发明人： Peter H. Voss
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.
摘要翻译：包括第一组存储器单元的存储器件，具有预编程状态的第二组存储器单元，以及被配置为访问包括在存储器单元的第一段中的数据的电路。当从第二组存储器单元读取数据时，该电路包括使能信号，以确定由第二组存储器单元输出的数据是否是在正常操作期间存储的预编程数据或数据。对于一个实施例，在第一组存储器单元和第二组存储器单元之间以一致的方式执行写入或从存储单元检索的数据。

68. 发明授权

US5822603A High bandwidth media processor interface for transmitting data in the form of packets with requests linked to associated responses by identification data 失效
标题翻译：高带宽媒体处理器接口，用于以具有通过标识数据链接到相关联的响应的请求的分组的形式发送数据
公开(公告)号：US5822603A
公开(公告)日：1998-10-13
申请号：US754827
申请日：1996-11-22
申请人： Craig Hansen , John Moussouris
发明人： Craig Hansen , John Moussouris
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/78 , H04N5/00 , H04N7/24 , G06F9/00
CPC分类号： G06F9/3802 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , G06F2212/2515 , Y02B60/1225
摘要： A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.
摘要翻译：一种通用的可编程媒体处理器，用于实时处理和传输音频，视频，无线电，图形，加密，认证和网络信息的媒体数据流。媒体处理器包含执行单元，其在整个媒体数据流中保持基本的峰值数据。执行单元包括动态分立的多精度算术单元，可编程开关和可编程扩展数学元素。高带宽外部接口以基本上峰值的速率将媒体数据流提供给通用寄存器文件和多精度执行单元。还提供了存储器管理单元以及指令和数据高速缓冲存储器/缓冲器。高带宽存储器控制器串联连接，为通用的可编程媒体处理器提供存储通道。通用的可编程媒体处理器被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。平行通用媒体处理器以分布式虚拟方式在整个网络中进行布置，以允许通过网络进行多处理器操作和资源共享。还提供了一种用于通过通信结构接收，处理和传送媒体数据流的方法。

69. 发明授权

US5794061A General purpose, multiple precision parallel operation, programmable media processor 失效
公开(公告)号：US5794061A
公开(公告)日：1998-08-11
申请号：US754829
申请日：1996-11-22
申请人： Craig Hansen , John Moussouris
发明人： Craig Hansen , John Moussouris
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/78 , H04N5/00 , H04N7/24 , G06F9/00
CPC分类号： G06F9/3802 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , G06F2212/2515 , Y02B60/1225
摘要： A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

70. 发明授权

US5794060A General purpose, multiple precision parallel operation, programmable media processor 失效
公开(公告)号：US5794060A
公开(公告)日：1998-08-11
申请号：US754826
申请日：1996-11-22
申请人： Craig Hansen , John Moussouris
发明人： Craig Hansen , John Moussouris
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/78 , H04N5/00 , H04N7/24 , G06F9/00
CPC分类号： G06F9/3802 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , G06F2212/2515 , Y02B60/1225
摘要： A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

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