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61. 发明申请

US20160041938A1 INFORMATION PROCESSING APPARATUS, STORAGE SYSTEM, AND COMPUTER-READABLE NON-TRANSITORY STORAGE MEDIUM STORING COMMUNICATION CONTROL PROGRAM 有权
标题翻译：信息处理设备，存储系统和计算机可读的非存储存储介质存储通信控制程序
公开(公告)号：US20160041938A1
公开(公告)日：2016-02-11
申请号：US14818814
申请日：2015-08-05
申请人： FUJITSU LIMITED
发明人： TAKANORI ISHII , Kazuko Sakurai , Yohei Nuno , Tatsuya Shinozaki
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4054 , G06F13/4282
摘要： An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range.
摘要翻译：信息处理装置包括：通过多个物理链路与另一装置通信的接口单元; 设置单元，其通过与所述另一设备进行协商来确定用于设置所述多个物理链路中的每一个的信号传输特性的设置参数的值，并且输出所述多个确定的所述设置参数的值，对应于所述多个物理链路之一的确定值; 以及判断单元，通过判断多个确定值中的最大值和最小值之间的差是否在预定范围内来判断多个确定值中的每一个是否正确。

62. 发明申请

US20150161069A1 HANDLING TWO SGPIO CHANNELS USING SINGLE SGPIO DECODER ON A BACKPLANE CONTROLLER 有权
标题翻译：在背板控制器上使用单个SGPIO解码器处理两个SGPIO通道
公开(公告)号：US20150161069A1
公开(公告)日：2015-06-11
申请号：US14100613
申请日：2013-12-09
申请人： AMERICAN MEGATRENDS, INC.
发明人： Kayalvizhi Dhandapani
IPC分类号： G06F13/40
CPC分类号： G06F13/4054 , G06F13/385 , G06F13/4068 , G06F13/409
摘要： An aspect of present disclosure relates to a computer-implemented method for handling two SGPIO channels by using one SGPIO decoder. The method includes: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data for monitoring and controlling a first and a second group of drive slots, (c) checking a clock signal having a first time period and a second time period, (d) forwarding the control commands and control data for the first group to the first group of drive slots during first time period, and forwarding the control commands and control data for the second group to the second group of drive slots during second time period, (e) receiving responses from first and second group of drive slots, respectively, and (f) sending the responses from first and second group of drive slots to the host computer.
摘要翻译：本公开的一个方面涉及一种通过使用一个SGPIO解码器来处理两个SGPIO信道的计算机实现的方法。该方法包括：（a）通过HBA建立背板控制器和主计算机之间的通信，（b）接收控制命令和控制数据，用于监视和控制第一组和第二组驱动器时隙，（c）检查时钟信号具有第一时间段和第二时间段，（d）在第一时间段期间将用于第一组的控制命令和控制数据转发到第一组驱动器时隙，并且将控制命令和控制数据转发到第二组在第二时间段期间的第二组驱动器插槽，（e）分别接收来自第一组和第二组驱动器插槽的响应，以及（f）将来自第一组和第二组驱动器时隙的响应发送到主机。

63. 发明申请

US20140115222A1 HIGH SPEED SERIAL PERIPHERAL INTERFACE SYSTEM 有权
标题翻译：高速串行外围接口系统
公开(公告)号：US20140115222A1
公开(公告)日：2014-04-24
申请号：US13657501
申请日：2012-10-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F13/20
CPC分类号： G06F13/4291 , G06F13/4054
摘要： A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.
摘要翻译：公开了一种包括总线适配器的串行外设接口（SPI）系统。总线适配器可以包括数据转换器，其可以适于从第一主输出外围输入（MOPI）线和来自SPI主器件的芯片选择线接收相应的第一和第二数据。数据转换器还可以适于交织第一和第二数据，并且数据转换器可以适于在第二MOPI线上与第二时钟信号同步地发送交错的第一和第二数据。总线适配器还可以包括适于产生第二时钟信号以传输到SPI外围设备的时钟速率调节器。第二时钟信号可以适于使得SPI外围设备能够读取所发送的数据。

64. 发明授权

US08645602B2 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US08645602B2
公开(公告)日：2014-02-04
申请号：US13179119
申请日：2011-07-08
申请人： Naoshi Ishikawa
发明人： Naoshi Ishikawa
IPC分类号： G06F13/00 , H04L27/00
CPC分类号： G06F13/4054
摘要： Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer.
摘要翻译：公开了一种可以获得总线访问的微计算机，而不管总线主机的频率与总线从站的频率之间的大小关系如何。 CPU根据具有可变频率的第一时钟进行操作。定时器根据第二时钟进行操作。频率转换逻辑电路通过主总线耦合到CPU，并通过外设I / O总线耦合到定时器。当第一时钟的频率高于第二时钟时，频率转换逻辑电路通过使用第一同步信号产生用于定时器的总线控制信号，该第一同步信号指示用于外围I / O总线的总线控制信号的改变定时。当第一时钟的频率低于第二时钟时，频率转换逻辑电路通过使用指示主总线的总线控制信号的改变定时的第二同步信号来产生CPU的总线控制信号。因此，无论CPU和定时器的频率之间的大小关系如何，都可以获得总线访问。

65. 发明授权

US07818528B2 System and method for asynchronous clock regeneration 有权
标题翻译：用于异步时钟再生的系统和方法
公开(公告)号：US07818528B2
公开(公告)日：2010-10-19
申请号：US11523453
申请日：2006-09-19
申请人： Thomas Hughes
发明人： Thomas Hughes
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00 , G06F1/04 , G06F1/12 , G06F1/14 , G06F1/24 , G06F5/06 , G11C7/04
CPC分类号： G06F13/4054
摘要： The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. The method further includes swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static. The method further includes regenerating a DQS (Data Strobe Signal) clock.
摘要翻译：本发明是异步时钟再生的方法。该方法包括使第一写指针和第二写指针同步，第一写指针是脱机写指针，第二写指针是在线写指针。所述方法还包括当所述位是静态时，使用所述第二写指针的至少一位将来自所述第一写指针的至少一位进行交换。该方法还包括再生DQS（数据选通信号）时钟。

66. 发明授权

US07805558B2 Method and system of controlling transfer speed of bus transactions 有权
标题翻译：控制总线交易传输速度的方法和系统
公开(公告)号：US07805558B2
公开(公告)日：2010-09-28
申请号：US11263356
申请日：2005-10-31
申请人： Lee Atkinson
发明人： Lee Atkinson
IPC分类号： G06F13/36
CPC分类号： G06F13/4054 , G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A method and system of controlling data transfer speed of bus transactions. At least some of the illustrative embodiments are methods comprising analyzing of a characteristic a first bus transaction that has yet to be applied to a bus, setting a first data transfer speed across the bus based on the characteristic of the first bus transaction, and sending the first bus transaction across the bus at the first data transfer speed.
摘要翻译：一种控制总线交易数据传输速度的方法和系统。说明性实施例中的至少一些是包括分析尚未应用于总线的第一总线事务的特征的方法，基于第一总线事务的特性来设置总线上的第一数据传输速度，并且发送第一次总线在总线上以第一个数据传输速度。

67. 发明授权

US07639561B2 Multi-port memory device having variable port speeds 有权
标题翻译：具有可变端口速度的多端口存储设备
公开(公告)号：US07639561B2
公开(公告)日：2009-12-29
申请号：US11694813
申请日：2007-03-30
申请人： Dongyun Lee , Myung Rai Cho , Sungjoon Kim
发明人： Dongyun Lee , Myung Rai Cho , Sungjoon Kim
IPC分类号： G11C8/18
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
摘要翻译：具有两个或多个端口的多端口存储器件，其中每个端口可以以不同的速度操作。多端口存储器件包含可通过两个或更多个端口访问的存储体。每个端口都应用两个时钟信号：系统时钟和端口时钟。系统时钟被应用于与存储体接口的端口逻辑，使得端口都以相对于存储体的公共速度运行。端口时钟应用于与每个端口相关联的时钟分频器电路。端口时钟被分为所需频率或保持在其原始频率。这样的配置允许端口以可以逐个端口为基础设置的不同速度进行操作。

68. 发明申请

US20090031060A1 BUS CONVERTER, SEMICONDUCTOR DEVICE, AND NOISE REDUCTION METHOD OF BUS CONVERTER AND SEMICONDUCTOR DEVICE 失效
标题翻译：总线转换器，半导体器件和总线转换器和半导体器件的噪声减少方法
公开(公告)号：US20090031060A1
公开(公告)日：2009-01-29
申请号：US12144956
申请日：2008-06-24
申请人： Masaharu Adachi
发明人： Masaharu Adachi
IPC分类号： G06F1/12
CPC分类号： G06F13/4054 , G06F13/4226 , G06F13/423
摘要： A bus converter is disclosed that converts a signal of a synchronous bus into a signal of an asynchronous bus. The bus converter includes a control signal generation unit that generates n control signals synchronized at different timings of a predetermined synchronization signal, where n is an integer of two or more; and an output unit that outputs the signal of the synchronous bus divided into n signal groups based on a control using the n control signals.
摘要翻译：公开了一种总线转换器，其将同步总线的信号转换为异步总线的信号。总线转换器包括控制信号生成单元，其产生在预定同步信号的不同定时同步的n个控制信号，其中n是2以上的整数; 以及输出单元，其基于使用n个控制信号的控制，输出被划分为n个信号组的同步总线的信号。

69. 发明授权

US07453909B2 Method for reducing the bus load in a synchronous data bus system 失效
标题翻译：减少同步数据总线系统总线负载的方法
公开(公告)号：US07453909B2
公开(公告)日：2008-11-18
申请号：US10538722
申请日：2002-12-27
申请人： Arild Wego , Pål Longva Hellum , Roar Malvig
发明人： Arild Wego , Pål Longva Hellum , Roar Malvig
IPC分类号： H04J3/00
CPC分类号： G06F13/4054 , G06F13/4072
摘要： The present invention is related to buffering between synchronous circuits communication via a global synchronous bus, and in particular an arrangement for reducing the busload in a TDM bus system by, in a preferred embodiment, introducing a local TEM data bus and an active buffer including a CPU controlled logic between the transceiver loads and the TDM bus. The active buffers in the TX and RX direction together provides a time delay for data travelling from a first local TDM bus out on the backplane TDM bus and back to a second local TDM of the exact duration of one TDM frame or an integer number of TDM frames.
摘要翻译：本发明涉及通过全球同步总线的同步电路通信之间的缓冲，特别是用于在TDM总线系统中减少总线负载的装置，在优选实施例中，引入局部TEM数据总线和包括收发器负载和TDM总线之间的CPU控制逻辑。 TX和RX方向上的主动缓冲器一起为在背板TDM总线上从第一本地TDM总线传出的数据提供时间延迟，并返回到一个TDM帧或整数TDM的确切持续时间的第二本地TDM 框架。

70. 发明授权

US07430624B2 High speed on-chip serial link apparatus and method 有权
标题翻译：高速片上串行连接装置及方法
公开(公告)号：US07430624B2
公开(公告)日：2008-09-30
申请号：US11242676
申请日：2005-10-04
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译：提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。因此，减少了本发明使用的复杂性和硅面积。该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

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