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61. 发明申请

US20080155177A1 Configuration of Host LBA Interface With Flash Memory 有权
标题翻译：使用闪存配置主机LBA接口
公开(公告)号：US20080155177A1
公开(公告)日：2008-06-26
申请号：US11616231
申请日：2006-12-26
申请人： Alan W. Sinclair , Barry Wright
发明人： Alan W. Sinclair , Barry Wright
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/04 , G06F2212/7206
摘要： Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.
摘要翻译：数据文件在具有物理存储器单元块的通常类型的闪存系统的连续逻辑地址空间接口（LBA接口）的一个或多个逻辑块内被分配地址。该分配可以由主机设备完成，主机设备通常但不一定生成数据文件。以减少物理存储器块内的文件数据的分段量的方式控制包含任何一个文件的数据的逻辑块的数量，从而保持良好的存储器性能。响应于学习与其连接的存储器的物理特性，主机可以配置地址空间的逻辑块。

62. 发明授权

US07356664B2 Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency 有权
标题翻译：用于将数据从存储器子系统传送到网络适配器以用于改善存储器子系统和PCI总线效率的方法和装置
公开(公告)号：US07356664B2
公开(公告)日：2008-04-08
申请号：US10621931
申请日：2003-07-17
申请人： Herman Dietrich Dierks, Jr. , Binh K. Hua , Sivarama K. Kodukula
发明人： Herman Dietrich Dierks, Jr. , Binh K. Hua , Sivarama K. Kodukula
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the memory, wherein the frame is transferred from the memory to the network adapter.
摘要翻译：一种用于将数据从存储器传送到网络适配器的方法，装置和计算机指令。接收到将数据传送到网络适配器的请求。为数据的起始地址设置偏移量以将数据与存储器中的帧的结尾对准，其中帧从存储器传送到网络适配器。

63. 发明申请

US20080010433A1 METHOD AND APPARATUS FOR EFFICIENTLY ACCESSING BOTH ALIGNED AND UNALIGNED DATA FROM A MEMORY 有权
标题翻译：从存储器中有效地访问两个对齐和对数据的方法和装置
公开(公告)号：US20080010433A1
公开(公告)日：2008-01-10
申请号：US11837241
申请日：2007-08-10
申请人： Eric Fluhr , Sheldon Levenstein
发明人： Eric Fluhr , Sheldon Levenstein
IPC分类号： G06F9/34
CPC分类号： G06F12/04 , G06F12/0846 , G06F12/0886
摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.
摘要翻译：一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

64. 发明授权

US07302525B2 Method and apparatus for efficiently accessing both aligned and unaligned data from a memory 失效
标题翻译：用于从存储器有效地访问对准和未对齐数据的方法和装置
公开(公告)号：US07302525B2
公开(公告)日：2007-11-27
申请号：US11055828
申请日：2005-02-11
申请人： Eric Jason Fluhr , Sheldon B. Levenstein
发明人： Eric Jason Fluhr , Sheldon B. Levenstein
IPC分类号： G06F12/02
CPC分类号： G06F12/04 , G06F12/0846 , G06F12/0886
摘要： A technique for improving access times when accessing memory, such as when accessing data from cache. By a unique manipulation and usage of a specified memory address in combination with the cache's internal organization, the address range required by the requested data can be covered by one odd and one even segment of the cache, where the odd segment is always at the base address created by the summation of the source operands and set to the odd segment, and the even address is created by summation of the source operands plus an offset value equivalent to the size of the cache line. This structural regularity is used to efficiently generate both the even and odd addresses in parallel to retrieve the desired data.
摘要翻译：一种用于在访问内存时改进访问时间的技术，例如从缓存访问数据时。通过与高速缓存的内部组织结合使用指定的存储器地址的独特操作和使用，所请求的数据所需的地址范围可以由高速缓存的一个奇数和一个偶数段覆盖，其中奇数段总是在基地地址由源操作数的总和创建并设置为奇数段，偶数地址是通过源操作数的加法加上与缓存行大小相等的偏移值来创建的。这种结构规律性用于有效地同时产生偶数和奇数地址以检索所需数据。

65. 发明申请

US20070245097A1 Memory compression method and apparatus for heterogeneous processor architectures in an information handling system 有权
标题翻译：用于信息处理系统中异构处理器架构的内存压缩方法和装置
公开(公告)号：US20070245097A1
公开(公告)日：2007-10-18
申请号：US11387999
申请日：2006-03-23
申请人： Michael Gschwind , Barry Minor
发明人： Michael Gschwind , Barry Minor
IPC分类号： G06F13/00
CPC分类号： G06F12/04 , G06F9/30178 , G06F12/08 , G06F2212/251 , G06F2212/253 , G06F2212/401
摘要： The disclosed heterogeneous processor compresses information to more efficiently store the information in a system memory coupled to the processor. The heterogeneous processor includes a general purpose processor core coupled to one or more processor cores that exhibit an architecture different from the architecture of the general purpose processor core. In one embodiment, the processor dedicates a processor core other than the general purpose processor core to memory compression and decompression tasks. In another embodiment, system memory stores both compressed information and uncompressed information.
摘要翻译：所公开的异构处理器压缩信息以更有效地将信息存储在耦合到处理器的系统存储器中。异构处理器包括耦合到一个或多个处理器核的通用处理器核心，其显示与通用处理器核心的架构不同的架构。在一个实施例中，处理器将除通用处理器核心之外的处理器核心专用于存储器压缩和解压缩任务。在另一个实施例中，系统存储器存储压缩信息和未压缩信息。

66. 发明申请

US20070079105A1 Data misalignment detection and correction in a computer system utilizing a mass storage subsystem 有权
标题翻译：在使用大容量存储子系统的计算机系统中的数据未对准检测和校正
公开(公告)号：US20070079105A1
公开(公告)日：2007-04-05
申请号：US11243716
申请日：2005-10-05
申请人： Mark Thompson
发明人： Mark Thompson
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G06F12/06 , G06F3/0608 , G06F3/064 , G06F3/0661 , G06F3/0689 , G06F11/3485 , G06F12/04
摘要： An embodiment of a data misalignment correction method for a mass storage drive array subsystem coupled to a computer operating system having input/output data block requests is provided. The data misalignment correction method includes automatically determining an amount of misalignment between a requested data block and a current data block alignment configuration, using the amount of misalignment to determine a preferred data bock alignment and realigning data block requests on the mass storage device according to the preferred data block alignment.
摘要翻译：提供了一种与具有输入/输出数据块请求的计算机操作系统耦合的大容量存储驱动器阵列子系统的数据未对准校正方法的实施例。数据未对准校正方法包括使用不对准量来自动确定所请求的数据块与当前数据块对齐配置之间的未对准量，以根据所述数据块对齐和重新对准大容量存储设备上的数据块请求优先数据块对齐。

67. 发明授权

US07136987B2 Memory configuration apparatus, systems, and methods 失效
标题翻译：内存配置设备，系统和方法
公开(公告)号：US07136987B2
公开(公告)日：2006-11-14
申请号：US10815173
申请日：2004-03-30
申请人： Inching Chen
发明人： Inching Chen
IPC分类号： G06F12/00 , G06F9/34
CPC分类号： G06F12/04 , G06F12/0646 , Y02D10/13
摘要： An apparatus and a system, as well as a method and article, may operate to control a bandwidth of a memory coupled to a plurality of data processing units responsive to protocol indications, such as a number of data processing units in use. In some embodiments, apparatus and systems, as well as methods and articles, may operate to select a memory access group size of about 2N memory banks responsive to receiving an indication of a change in a protocol type, wherein the group is selected from a number B of banks, and N is associated with the protocol type.
摘要翻译：装置和系统以及方法和文章可以操作以响应于诸如使用的数据处理单元的协议指示来控制耦合到多个数据处理单元的存储器的带宽。在一些实施例中，装置和系统以及方法和物品可以操作以响应于接收到协议类型的变化的指示来选择大约2个N个存储体的存储器存取组大小，其中所述组是从数量B的组中选择的，并且N与所述协议类型相关联。

68. 发明申请

US20060230198A1 Data processing circuit, data processing method and image forming apparatus 审中-公开
标题翻译：数据处理电路，数据处理方法和图像形成装置
公开(公告)号：US20060230198A1
公开(公告)日：2006-10-12
申请号：US11095095
申请日：2005-03-30
申请人： Hidenori Kobayashi
发明人： Hidenori Kobayashi
IPC分类号： G06F13/38
CPC分类号： G06F12/04 , H04N1/32358 , H04N2201/0471 , H04N2201/04722
摘要： The present invention, when a fraction for a bus width of a storage area is changed, stores a RAM address storing data immediately before or a RAM address for inputting the changed information in an exclusive register, thereby saves the storage area of data. When calculating stored data together, there is no need to always add the high-order address which is a fraction to calculation, so that the processing time is shortened.
摘要翻译：本发明当存储区域的总线宽度的分数被改变时，将存储紧接在前的数据的RAM地址或用于将改变的信息输入的RAM地址存储在专用寄存器中，从而保存数据的存储区域。在一起计算存储数据时，不需要总是添加作为计算的分数的高阶地址，从而缩短处理时间。

69. 发明申请

US20060010304A1 Systems for loading unaligned words and methods of operating the same 有权
标题翻译：用于装载未对齐字的系统及其操作方法
公开(公告)号：US20060010304A1
公开(公告)日：2006-01-12
申请号：US10922242
申请日：2004-08-19
申请人： Mark Homewood , Paolo Faraboschi
发明人： Mark Homewood , Paolo Faraboschi
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30145 , G06F12/04
摘要： A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.
摘要翻译：一种从存储器中指定的未对齐字地址加载未对齐字的方法，所述未对齐字包括与字边界交叉的多个索引部分，所述方法包括：加载从所述指定的四边形对齐的字地址开始的第一对齐字未对齐的字地址; 识别表示未对齐字地址相对于对齐字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 并且使用所识别的索引来组合第一和第二对齐字的索引部分以构造未对齐字。

70. 发明授权

US06970993B2 Architecture to relax memory performance requirements 有权
标题翻译：架构放松内存性能要求
公开(公告)号：US06970993B2
公开(公告)日：2005-11-29
申请号：US10658058
申请日：2003-09-08
申请人： Bruce L. Troutman , Russell B. Lloyd , Randal Q. Thornley
发明人： Bruce L. Troutman , Russell B. Lloyd , Randal Q. Thornley
IPC分类号： G06F12/04 , G06F12/00
CPC分类号： G06F12/04
摘要： The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.
摘要翻译：本发明提供一种允许存储可变长度指令而不浪费存储空间的存储架构。一个，两个和三个字节的指令都可以在单个提取中检索。该示例性实施例将存储块划分成具有一些特殊寻址电路的两个x16存储器。该结构将内存逻辑排列成四行字节列中的每一行。对于这些x16存储器中的第一个，提供了完整的地址。如果地址在第二x16存储器的两列内，则还将向第二x16存储器提供完整地址。如果地址是x16存储器中的第一个，则第二x16存储器代替地接收指定行的地址部分。这导致双行访问，最后一个或两个字节的3字节指令由第一个字节之上的行提供。最终的效果是所有的物理内存物理空间都用于程序代码，24位访问中没有浪费。

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