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61. 发明申请

US20150198658A1 METHOD AND EQUIPMENT FOR TESTING SEMICONDUCTOR APPARATUSES SIMULTANEOUSLY AND CONTINUOUSLY 审中-公开
标题翻译：同时并连续测试半导体器件的方法和设备
公开(公告)号：US20150198658A1
公开(公告)日：2015-07-16
申请号：US14669334
申请日：2015-03-26
申请人： Samsung Electronics Co., Ltd.
发明人： Eun-sik Kim , Kil-yeon Kim , Yun-bo Yang , Kui-hyun Ro , Heon-gwon Lee , Young-jae Jung
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2851 , G01R31/2607 , G01R31/2855 , G01R31/3187
摘要： A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, Which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board.
摘要翻译：一种用于测试多个半导体器件的方法，所述方法包括在第一测试板上安装多个半导体器件，其中所述多个半导体器件包括测试电路，将测试软件加载到测试电路中，通过使用测试电路基于测试软件对多个半导体装置进行自检，并且从第一测试板中去除已经完成了自检的多个半导体装置。在完成测试软件的加载之后，在第一测试板上对多个半导体设备执行自检，将测试软件加载到第二测试板上的多个半导体设备的测试电路中。

62. 发明申请

US20150130485A1 MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL 审中-公开
标题翻译：从专用测试电路到功率终端的调制测试消息
公开(公告)号：US20150130485A1
公开(公告)日：2015-05-14
申请号：US14599849
申请日：2015-01-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/31723 , G01R31/2851 , G01R31/2884 , G01R31/31721 , G01R31/3177 , G01R31/31917 , G01R31/31919
摘要： The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
摘要翻译：本公开描述了一种用于将设备的电源和接地终端用作设备的测试和/或调试接口的新颖方法和装置。根据本公开，通过施加到设备的电源端子的DC电压来调制消息，以向设备输入测试/调试消息并从设备输出测试/调试消息。本公开有利地允许在没有任何共享或专用测试或调试接口终端的设备的情况下测试和/或调试设备。

63. 发明授权

US09000789B2 Method and equipment for testing semiconductor apparatuses simultaneously and continuously 有权
标题翻译：同时连续测试半导体设备的方法和设备
公开(公告)号：US09000789B2
公开(公告)日：2015-04-07
申请号：US13240528
申请日：2011-09-22
申请人： Eun-sik Kim , Kil-yeon Kim , Yun-bo Yang , Kui-hyun Ro , Heon-gwon Lee , Young-jae Jung
发明人： Eun-sik Kim , Kil-yeon Kim , Yun-bo Yang , Kui-hyun Ro , Heon-gwon Lee , Young-jae Jung
IPC分类号： G01R31/3187
CPC分类号： G01R31/2851 , G01R31/2607 , G01R31/2855 , G01R31/3187
摘要： A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board.
摘要翻译：一种用于测试多个半导体器件的方法，所述方法包括在第一测试板上安装多个半导体器件，其中所述多个半导体器件包括测试电路，将测试软件加载到测试电路中，通过使用测试电路基于测试软件对多个半导体装置进行自检，并且从第一测试板去除完成了自检的多个半导体装置。在完成测试软件的加载之后，在第一测试板上对多个半导体设备执行自检，将测试软件加载到第二测试板上的多个半导体设备的测试电路中。

64. 发明授权

US08990648B2 Optimized synchronous scan flip flop circuit 有权
标题翻译：优化同步扫描触发电路
公开(公告)号：US08990648B2
公开(公告)日：2015-03-24
申请号：US13432004
申请日：2012-03-28
申请人： Ravi Lakshmipathy , Balaji Upputuri
发明人： Ravi Lakshmipathy , Balaji Upputuri
IPC分类号： G01R31/28 , G06F11/00 , G01R31/3187 , G01R31/3185 , G01R31/3177 , G06F11/26 , G11C29/32
CPC分类号： G01R31/318541 , G01R31/2851 , G01R31/3177 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/3187 , G06F11/26 , G11C29/32
摘要： According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.
摘要翻译：根据至少一个示例性实施例，提供了同步有效高复位扫描触发器。同步有效高复位扫描触发器可以包括数据输入，串行输入，测试使能输入，复位输入，时钟输入，器件输出。它还可以包括被配置为接收串行输入和测试使能输入的AND门，以及被配置为接收数据输入的多路复用器和从与门接收的第一输出信号。复用器可响应用于在功能模式下复位触发器的复位输入而工作，并允许在测试模式下的扫描测试。同步有效高复位扫描触发器还可以包括存储元件，其被配置为接收从多路复用器接收的第二输出信号，并响应于从时钟输入接收到的时钟信号而可操作。

65. 发明授权

US08972809B2 Test messaging and control circuitry coupled to power pad 有权
标题翻译：耦合到电源板的测试消息和控制电路
公开(公告)号：US08972809B2
公开(公告)日：2015-03-03
申请号：US13941844
申请日：2013-07-15
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/319
CPC分类号： G01R31/31723 , G01R31/2851 , G01R31/2884 , G01R31/31721 , G01R31/3177 , G01R31/31917 , G01R31/31919
摘要： The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
摘要翻译：本公开描述了一种用于将设备的电源和接地终端用作设备的测试和/或调试接口的新颖方法和装置。根据本公开，通过施加到设备的电源端子的DC电压来调制消息，以向设备输入测试/调试消息并从设备输出测试/调试消息。本公开有利地允许在没有任何共享或专用测试或调试接口终端的设备的情况下测试和/或调试设备。

66. 发明申请

US20150025830A1 METHODS AND SYSTEMS TO MEASURE A SIGNAL ON AN INTEGRATED CIRCUIT DIE 审中-公开
标题翻译：用于测量集成电路的信号的方法和系统
公开(公告)号：US20150025830A1
公开(公告)日：2015-01-22
申请号：US14508082
申请日：2014-10-07
申请人： VINU K. ELIAS
发明人： VINU K. ELIAS
IPC分类号： G01R31/3183 , G01R31/28
CPC分类号： G01R31/3183 , G01R31/2851 , G01R31/2884
摘要： Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement ent circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.
摘要翻译：用于测量集成电路管芯上的信号的方法和系统。片上测量电路可以测量相对于离线生成的参考信号的片上信号，其可以包括一系列增加的电压步长。片上测量电路可以连续地比较裸片上信号和离群芯片产生的参考信号的电压，并且可以在片外参考信号超过片上信号时产生指示。测量电路可以从除被测量的裸片上信号之外的电压源产生指示，和/或可产生相对较大的电压摆幅的指示。该指示可以被输出用于评估，例如用于测试，调试，表征和/或操作监视。可以提供单位增益模拟缓冲器来抽取靠近感兴趣的节点的芯片上信号，这可以在片上测量电路内实现。

67. 发明申请

US20140333341A1 TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES 有权
标题翻译：测试半导体器件中的保险丝配置
公开(公告)号：US20140333341A1
公开(公告)日：2014-11-13
申请号：US14250191
申请日：2014-04-10
申请人： RAMBUS INC.
发明人： Adrian E. Ong , Paul Fuller , Nick van Heel , Mark Thomann
IPC分类号： G01R31/28
CPC分类号： G01R31/31722 , G01R31/2851 , G01R31/31723 , H01L2224/05554 , H01L2224/48137 , H01L2224/48145 , H01L2924/00012
摘要： Methods, systems, and apparatus for testing semiconductor devices.
摘要翻译：用于测试半导体器件的方法，系统和设备。

68. 发明授权

US08850279B2 IC test linking module with augmentation instruction shift register 有权
标题翻译： IC测试链接模块与增补指令移位寄存器
公开(公告)号：US08850279B2
公开(公告)日：2014-09-30
申请号：US14190314
申请日：2014-02-26
申请人： Texas Instruments Incorporated
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使得测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

69. 发明授权

US08790134B2 Connector, cable assembly, and semiconductor testing device 有权
标题翻译：连接器，电缆组件和半导体测试装置
公开(公告)号：US08790134B2
公开(公告)日：2014-07-29
申请号：US13378004
申请日：2010-06-30
申请人： Nobumasa Motohashi , Akinori Mizumura , Toshihiro Niitsu , Teruhito Suzuki , Shin Sakiyama
发明人： Nobumasa Motohashi , Akinori Mizumura , Toshihiro Niitsu , Teruhito Suzuki , Shin Sakiyama
IPC分类号： H01R9/05
CPC分类号： H01R9/0527 , G01R31/2851 , H01R9/038 , H01R12/721 , H01R2201/20
摘要： The connector includes an enclosure including insertion holes formed therein, into which tip end portions of coaxial cables provided with signal terminals and with ground terminals arranged at parts of peripheries of the signal terminals are inserted, and auxiliary ground conductors, which are retained by the enclosure, are electrically connected to the ground terminals, and are arranged at other parts of the peripheries of the signal terminals.
摘要翻译：连接器包括一个包括形成在其中的插入孔的外壳，设有信号端子的同轴电缆的末端部分和布置在信号端子周边部分的接地端子插入其中，辅助接地导体由外壳保持，电连接到接地端子，并且布置在信号端子的周边的其他部分。

70. 发明申请

US20140195183A1 METHOD AND SYSTEM FOR ESTIMATING A DIFFUSION POTENTIAL OF A DIFFUSIVE PROPERTY 审中-公开
标题翻译：用于估计扩散性能的扩散潜力的方法和系统
公开(公告)号：US20140195183A1
公开(公告)日：2014-07-10
申请号：US14237259
申请日：2012-04-05
申请人： Harish Chandra Rajput , Andrew Labun , Thomas Edward Johnson
发明人： Harish Chandra Rajput , Andrew Labun , Thomas Edward Johnson
IPC分类号： G01R31/28
CPC分类号： G01R31/2851 , G01R31/2628 , G06F17/5036
摘要： Described herein are a method, system, and computer readable medium for estimating a diffusion potential (such as temperature) of a diffusive property (such as thermal energy, referred to herein as “heat”). The method includes modeling as a circuit a diffusion region having two subregions to which the diffusive property is introduced at different rates and through which the diffusive property linearly diffuses. The nodes of the circuit include a dividing node that divides branches of the circuit that model the two subregions. A circuit potential at one of the nodes of the circuit corresponds to the diffusion potential at a location within the diffusion region. The diffusion potential at the location within the diffusion region is estimated by simulating operating of the circuit and determining the circuit potential at the node of the circuit.
摘要翻译：这里描述了一种用于估计扩散性（例如热能，在本文中称为“热”）的扩散电位（例如温度）的方法，系统和计算机可读介质。该方法包括将具有两个子区域的扩散区域建模为漫射特性以不同的速率被引入的扩散区域，扩散性质线性扩散。该电路的节点包括一个分割节点，该分割节点分割对两个子区域建模的电路的分支。电路的一个节点处的电路电位对应于扩散区域内的扩散电位。通过模拟电路的运行并确定电路节点处的电路电位来估计扩散区内位置处的扩散电位。

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