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61. 发明授权

US07880446B2 Adaptive frequency compensation for DC-to-DC converter 有权
标题翻译： DC-DC转换器的自适应频率补偿
公开(公告)号：US07880446B2
公开(公告)日：2011-02-01
申请号：US11352031
申请日：2006-02-10
申请人： Lu Chen , Bruno Ferrario
发明人： Lu Chen , Bruno Ferrario
IPC分类号： H01M10/46
CPC分类号： H02M3/156 , H02M2001/0025
摘要： One embodiment of the invention is a compensation circuit that includes a comparator that is coupled to receive a reference voltage. The compensation circuit can also include a capacitance coupled to receive a feedback voltage associated with an output voltage of a converter. Furthermore, the compensation circuit can include an adjustable resistance that is coupled to the capacitance and to the comparator.
摘要翻译：本发明的一个实施例是一种补偿电路，其包括耦合以接收参考电压的比较器。补偿电路还可以包括耦合以接收与转换器的输出电压相关联的反馈电压的电容。此外，补偿电路可以包括耦合到电容和比较器的可调电阻。

62. 发明授权

US07868381B1 Structures of and methods of fabricating trench-gated MIS devices 有权
标题翻译：沟槽栅MIS设备的结构和方法
公开(公告)号：US07868381B1
公开(公告)日：2011-01-11
申请号：US11982906
申请日：2007-11-05
申请人： Anup Bhalla , Domon Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
发明人： Anup Bhalla , Domon Pitzer , Jacek Korec , Xiaorong Shi , Sik Lui
IPC分类号： H01L27/108
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/088 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/8725 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
摘要翻译：在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。这避免了沟槽上角处的应力问题。栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

63. 发明申请

US20100019751A1 ADAPTIVE FREQUENCY COMPENSATION FOR DC-to-DC CONVERTER 有权
标题翻译： DC-DC转换器的自适应频率补偿
公开(公告)号：US20100019751A1
公开(公告)日：2010-01-28
申请号：US12571194
申请日：2009-09-30
申请人： Lu Chen , Bruno Ferrario
发明人： Lu Chen , Bruno Ferrario
IPC分类号： G05F1/10
CPC分类号： H02M3/156 , H02M2001/0025
摘要： One embodiment of the invention is a compensation circuit that includes a comparator that is coupled to receive a reference voltage. The compensation circuit can also include a capacitance coupled to receive a feedback voltage associated with an output voltage of a converter. Furthermore, the compensation circuit can include an adjustable resistance that is coupled to the capacitance and to the comparator.
摘要翻译：本发明的一个实施例是一种补偿电路，其包括耦合以接收参考电压的比较器。补偿电路还可以包括耦合以接收与转换器的输出电压相关联的反馈电压的电容。此外，补偿电路可以包括耦合到电容和比较器的可调电阻。

64. 发明授权

US07642164B1 Method of forming self aligned contacts for a power MOSFET 有权
标题翻译：形成功率MOSFET自对准触点的方法
公开(公告)号：US07642164B1
公开(公告)日：2010-01-05
申请号：US10951831
申请日：2004-09-27
申请人： Robert Q. Xu , Jacek Korec
发明人： Robert Q. Xu , Jacek Korec
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L29/407 , H01L29/7813
摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.
摘要翻译：公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。该方法还包括凹陷形成在沟槽中的多晶硅插塞，其位于有源区域中，以在多晶硅插塞之上形成凹陷，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成一个绝缘体，从而施加第四张照片抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦的表面氧化物按钮。此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

65. 发明申请

US20090200578A1 SELF-REPAIRING FIELD EFFECT TRANSISITOR 审中-公开
标题翻译：自我修复场效应信号
公开(公告)号：US20090200578A1
公开(公告)日：2009-08-13
申请号：US12030719
申请日：2008-02-13
申请人： Robert Xu
发明人： Robert Xu
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/7802 , H01L23/5256 , H01L27/088 , H01L29/41741 , H01L29/66734 , H01L29/7813 , H01L29/8083 , H01L2924/0002 , H01L2924/00
摘要： A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
摘要翻译：根据一个实施例的自修复场效应晶体管（FET）器件包括多个具有熔丝链的FET单元。熔断体适于在相应电池中的高电流事件期间吹动。

66. 发明申请

US20090174055A1 Leadless Semiconductor Packages 有权
标题翻译：无铅半导体封装
公开(公告)号：US20090174055A1
公开(公告)日：2009-07-09
申请号：US12401549
申请日：2009-03-10
申请人： Frank Kuo
发明人： Frank Kuo
IPC分类号： H01L23/52
CPC分类号： H01L21/565 , H01L23/3107 , H01L2924/0002 , H01L2924/00
摘要： An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (411) to die pads in cavities (41-45, 51-55) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (412-414) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (46-49, 56-59) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.
摘要翻译：用于无引线半导体封装的封装技术包括：（a）将多个管芯（411）附接到引线框架的空腔（41-45,51-55）中的管芯焊盘，所述空腔布置成列和列的矩阵; （b）将所述裸片电连接到所述引线框架的多个导电部分（412-414）; 以及（c）通过所述引线框架的多个纵向门（46-49,56-59）沿着所述列将模制材料纵向注射到所述空腔中，以将所述模具封装在所述空腔中，所述纵向浇口位于所述空腔之间，。

67. 发明授权

US07494876B1 Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same 失效
标题翻译：在沟槽底部具有厚多晶硅绝缘层的沟槽门式MIS器件及其制造方法
公开(公告)号：US07494876B1
公开(公告)日：2009-02-24
申请号：US11112403
申请日：2005-04-21
申请人： Frederick Perry Giles , Kam Hong Lui
发明人： Frederick Perry Giles , Kam Hong Lui
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： In a trench-gated MIS semiconductor device, a slug of undoped polysilicon is deposited at the bottom of the trench to protect the gate oxide in this area against the high electric fields that can occur in this area. The slug is formed over a thick oxide layer at the bottom of the trench. A process of fabricating the MOSFET includes the steps of growing a thick oxide layer on the sidewalls and bottom of the trench, depositing a polysilicon layer which remains undoped, etching the polysilicon layer to form the plug, etching the exposed portion of the thick oxide layer, growing a gate oxide layer and an oxide layer over the plug, and depositing and doping a polysilicon layer which serves as the gate electrode. In an alternative embodiment, the oxide layer overlying the plug is etched before the gate polysilicon is deposited such that the dopant introduced into the gate polysilicon migrates into the polysilicon plug. In this embodiment, the polysilicon plug is in electrical contact with the gate polysilicon layer and is separated from the drain by the thick oxide layer.
摘要翻译：在沟槽门控MIS半导体器件中，未掺杂的多晶硅块被沉积在沟槽的底部，以保护该区域中的栅极氧化物抵抗可能在该区域中发生的高电场。块状物形成在沟槽底部的厚氧化物层上。制造MOSFET的过程包括以下步骤：在沟槽的侧壁和底部生长厚的氧化物层，沉积保留未掺杂的多晶硅层，蚀刻多晶硅层以形成插塞，蚀刻厚氧化物层的暴露部分在插头上生长栅极氧化层和氧化物层，以及沉积和掺杂用作栅电极的多晶硅层。在替代实施例中，在栅极多晶硅被沉积之前蚀刻覆盖在插塞上的氧化物层，使得引入到栅极多晶硅中的掺杂剂迁移到多晶硅插塞中。在该实施例中，多晶硅插塞与栅极多晶硅层电接触并且通过厚氧化物层与漏极分离。

68. 发明申请

US20080246081A1 Self-Aligned Trench MOSFET and Method of Manufacture 有权
标题翻译：自对准沟槽MOSFET及其制造方法
公开(公告)号：US20080246081A1
公开(公告)日：2008-10-09
申请号：US12015723
申请日：2008-01-17
申请人： Jian Li , Kuo-In Chen , Kyle Terril
发明人： Jian Li , Kuo-In Chen , Kyle Terril
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/7813
摘要： A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.
摘要翻译：根据一个实施例的沟槽金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域，设置在漏极区域上方的多个栅极区域，多个栅极绝缘体区域，每个栅极绝缘体区域围绕相应的所述多个栅极区域中的一个，设置在所述多个栅极绝缘体区域之间的凹入台面中的多个源极区域，设置在所述多个栅极绝缘体区域之间和所述多个源极区域之间的凹入台面中的多个主体区域，以及漏区。 MOSFET还包括设置在与多个源极区域相邻的每个主体区域中的多个体接触区域，多个源/体接触间隔物，其设置在凹入的台面之上的多个栅极绝缘体区域之间，设置在源极/ 以及多个源/体接触插塞，其设置在源/体接触间隔件之间并将源/体接触件耦合到多个体接触区域和多个源极区域。

69. 发明申请

US20080135872A1 Trench polysilicon diode 有权
标题翻译：沟槽多晶硅二极管
公开(公告)号：US20080135872A1
公开(公告)日：2008-06-12
申请号：US12009379
申请日：2008-01-17
申请人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
发明人： Qufei Chen , Robert Xu , Kyle Terrill , Deva Pattanayak
IPC分类号： H01L29/74
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L27/0814 , H01L29/66727 , H01L29/66734 , H01L29/7808 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.
摘要翻译：本发明的实施例包括制造沟槽晶体管的方法。该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

70. 发明授权

US07151036B1 Precision high-frequency capacitor formed on semiconductor substrate 失效
公开(公告)号：US07151036B1
公开(公告)日：2006-12-19
申请号：US10456018
申请日：2003-06-05
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/8242
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.

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