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61. 发明申请

US20120176711A1 METHOD AND APPARATUS FOR SWITCHED ELECTROSTATIC DISCHARGE PROTECTION 有权
标题翻译：用于切换静电放电保护的方法和装置
公开(公告)号：US20120176711A1
公开(公告)日：2012-07-12
申请号：US13175387
申请日：2011-07-01
申请人： Raymond J. Farbarik , Jeremy Stephens , Gerald J. Twomey
发明人： Raymond J. Farbarik , Jeremy Stephens , Gerald J. Twomey
IPC分类号： H02H3/20
CPC分类号： H02H9/046
摘要： One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.
摘要翻译：一个实施例包括集成电路，其包括输入电路，包括第一阳极和第一阴极的第一二极管，其中第一阴极耦合到第一电压，第一阳极经由第一机械开关耦合到节点处的输入电路，第二二极管，包括第二阳极和第二阴极，其中第二阴极经由第二机械开关耦合到节点，第二阳极耦合到地和耦合到集成电路和节点之间的输入电路的电阻器，其中在第一操作模式中，第一机械开关和第二机械开关导通，并且在第二操作模式中，第一和第二机械开关是不导通的。

62. 发明授权

US08170724B2 Systems and associated methods for controllably cooling computer components 有权
标题翻译：用于可控冷却计算机组件的系统和相关方法
公开(公告)号：US08170724B2
公开(公告)日：2012-05-01
申请号：US12029124
申请日：2008-02-11
申请人： Douglas P. Kelley , Wade J. Doll , Alexander I. Yatskov
发明人： Douglas P. Kelley , Wade J. Doll , Alexander I. Yatskov
IPC分类号： G05D23/00
CPC分类号： H05K7/20836 , H05K7/20736 , H05K7/20781 , H05K7/2079
摘要： Computer systems and associated methods for cooling computer components are disclosed herein. One embodiment of a computer system includes a computer cabinet having an air inlet spaced apart from an air outlet. The computer system also includes heat exchangers positioned in the computer cabinet, and a heat removal system in fluid communication with the heat exchangers. The computer system additionally includes at least one sensor for monitoring heat transfer between the computer cabinet and the room. The computer system further includes a control system operatively coupled to the at least one sensor, the control system including a computer-readable medium holding instructions for determining whether heat transfer between the computer cabinet and the room is balanced based on information from the sensor, and if not, adjusting a parameter to balance the heat transfer.
摘要翻译：本文公开了用于冷却计算机部件的计算机系统和相关方法。计算机系统的一个实施例包括具有与空气出口间隔开的空气入口的计算机机柜。计算机系统还包括位于计算机机柜中的热交换器，以及与热交换器流体连通的散热系统。计算机系统还包括至少一个用于监测计算机机柜和房间之间的热传递的传感器。所述计算机系统还包括可操作地耦合到所述至少一个传感器的控制系统，所述控制系统包括计算机可读介质，所述计算机可读介质保持用于基于来自所述传感器的信息来确定所述计算机机柜和房间之间的热传递是否平衡的指令，如果没有，调整参数以平衡传热。

63. 发明申请

US20110271259A1 SYSTEMS AND METHODS FOR DEBUGGING APPLICATIONS USING DUAL CODE GENERATION 有权
标题翻译：使用双代码生成调试应用程序的系统和方法
公开(公告)号：US20110271259A1
公开(公告)日：2011-11-03
申请号：US12771432
申请日：2010-04-30
申请人： Robert Warren Moench , Robert Cushman Clark
发明人： Robert Warren Moench , Robert Cushman Clark
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/362 , G06F8/443 , G06F11/3628
摘要： Systems and methods provide a debugger that debugs code using two versions of code, an optimized and a debuggable version of object code for subroutines, methods or functions. The debugger causes the appropriate version of the code to be executed depending on whether debug commands have been applied with respect to particular subroutines, methods or functions.
摘要翻译：系统和方法提供了一个调试器，可以使用两个版本的代码调试代码，优化的和可调试版本的子例程，方法或函数的目标代码。根据调试命令是否针对特定子程序，方法或函数进行应用，调试器将导致执行代码的适当版本。

64. 发明申请

US20110150136A1 DUTY CYCLE COMPENSATING DIGITAL DATA RECEIVER 审中-公开
标题翻译：占空比数字数据接收器
公开(公告)号：US20110150136A1
公开(公告)日：2011-06-23
申请号：US12643532
申请日：2009-12-21
申请人： Roger A. Bethard
发明人： Roger A. Bethard
IPC分类号： H04L27/00
CPC分类号： H04L25/069 , H04L7/0331
摘要： A data communication receiver includes an interface operable to receive at least one incoming data signal. A transition point tracker is operable to track data transition points of the data signal, and a data sampler is operable to sample the data signal at a desired sampling point between transition points.
摘要翻译：数据通信接收机包括可操作以接收至少一个输入数据信号的接口。转换点跟踪器可操作以跟踪数据信号的数据转换点，并且数据采样器可操作以在转换点之间的期望采样点对数据信号进行采样。

65. 发明申请

US20110010522A1 MULTIPROCESSOR COMMUNICATION PROTOCOL BRIDGE BETWEEN SCALAR AND VECTOR COMPUTE NODES 审中-公开
标题翻译：标准和矢量电脑节目之间的多媒体通信协议桥
公开(公告)号：US20110010522A1
公开(公告)日：2011-01-13
申请号：US12814118
申请日：2010-06-11
申请人： Dennis C. Abts , Peter M. Klausler , James Nowicki
发明人： Dennis C. Abts , Peter M. Klausler , James Nowicki
IPC分类号： G06F13/36 , G06F15/76 , G06F9/02
CPC分类号： G06F15/17375
摘要： A multiprocessor computer system includes a plurality of processor nodes coupled by a direct processor interconnect network, and a plurality of processor nodes coupled by an indirect processor interconnect network. A bridge directly couples the direct processor interconnect network and the indirect processor interconnect network.
摘要翻译：多处理器计算机系统包括通过直接处理器互连网络耦合的多个处理器节点和由间接处理器互连网络耦合的多个处理器节点。桥接器直接耦合直接处理器互连网络和间接处理器互连网络。

66. 发明申请

US20100318747A1 ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING 失效
标题翻译： ATOMIC MEMORY OPERATION CACHE COMPOROCO WITH OPPORTUNISTIC COMBINING
公开(公告)号：US20100318747A1
公开(公告)日：2010-12-16
申请号：US12484165
申请日：2009-06-12
申请人： Dennis C. Abts , Steven L. Scott
发明人： Dennis C. Abts , Steven L. Scott
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/526 , G06F12/0815
摘要： An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.
摘要翻译：原子存储器操作高速缓存包括用于缓存原子存储器操作数据的高速缓存存储器，写入定时器和高速缓存控制器。高速缓存控制器可操作以在写定时器期满时，用存储在高速缓存存储器中的一个或多个脏原子存储器操作高速缓存条目来更新主存储器，并且还可操作以用存储的一个或多个脏原子存储器操作高速缓存条目来更新主存储器在从高速缓存存储器中消除一个或多个脏原子存储器操作高速缓存条目之后的缓存存储器中。

67. 发明申请

US20100318591A1 INCLUSIVE OR BIT MATRIX TO COMPARE MULTIPLE CORRESPONDING SUBFIELDS 有权
标题翻译：包含或比特矩阵来比较多个相应的子文件
公开(公告)号：US20100318591A1
公开(公告)日：2010-12-16
申请号：US12814101
申请日：2010-06-11
申请人： William F. Long
发明人： William F. Long
IPC分类号： G06F7/04 , G06F17/16
CPC分类号： G06F7/02 , G06F7/57 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F17/16
摘要： A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern.
摘要翻译：计算机系统可操作以使用填充有图案元素的第一矩阵和参考图案之间的比特矩阵比较函数来识别在两个数据元素中不同的子场。

68. 发明授权

US07852836B2 Reduced arbitration routing system and method 有权
标题翻译：减少仲裁路由系统和方法
公开(公告)号：US07852836B2
公开(公告)日：2010-12-14
申请号：US11932413
申请日：2007-10-31
申请人： Steven L. Scott , Dennis C. Abts , Gregory Hubbard
发明人： Steven L. Scott , Dennis C. Abts , Gregory Hubbard
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , G06F11/0724 , G06F11/0781 , H04L45/40 , H04L45/54 , H04L45/60 , H04L45/742
摘要： A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.
摘要翻译：一种用于在具有由网络连接的多个节点的系统中将分组从一个节点路由到另一个节点的系统和方法。在每个节点中提供节点路由器，其中节点路由器包括多个网络端口，包括第一和第二网络端口，其中每个网络端口包括用于与其他网络节点之一通信的通信信道，多个虚拟通道输入缓冲器和多个虚拟通道暂存缓冲器，其中每个虚拟通道分段缓冲器从多个输入缓冲器之一接收数据。

69. 发明授权

US07826996B2 Memory-daughter-card-testing apparatus and method 有权
标题翻译：记忆子卡测试仪和方法
公开(公告)号：US07826996B2
公开(公告)日：2010-11-02
申请号：US11679175
申请日：2007-02-26
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G01C31/00 , G06F11/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一个MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

70. 发明申请

US20100115236A1 HIERARCHICAL SHARED SEMAPHORE REGISTERS 审中-公开
标题翻译：分层分析仪
公开(公告)号：US20100115236A1
公开(公告)日：2010-05-06
申请号：US12263305
申请日：2008-10-31
申请人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
发明人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30101 , G06F9/52
摘要： A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.
摘要翻译：具有多个处理元件的多处理器计算机系统包括一个或多个核心级别分层共享信号量寄存器，其中每个核心级别分层共享信号量寄存器耦合到不同的处理器核心。每个分层共享信号量寄存器对于在耦合的处理器核上执行的多个流中的每一个是可写的。一个或多个芯片级别分层共享信号量寄存器也耦合到多个处理器核，每个芯片级分级共享信号量寄存器可写入多个处理器核心中的每一个。

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