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61. 发明申请

US20090141539A1 RADIATION TOLERANT SRAM BIT 有权
标题翻译：辐射稳定SRAM位
公开(公告)号：US20090141539A1
公开(公告)日：2009-06-04
申请号：US12345388
申请日：2008-12-29
申请人： John McCollum
发明人： John McCollum
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/4125 , G11C5/005
摘要： In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
摘要翻译：在集成电路中，包括具有输入和输出的第一反相器的辐射耐受静态随机存取存储器件，具有输入和输出的第二反相器。第一电阻器耦合在第一反相器的输出端和第二反相器的输入端之间。第二电阻耦合在第二反相器的输出端和第一反相器的输入端之间。第一写入晶体管耦合到第一反相器的输出，并且具有耦合到第一组写入控制信号的源的栅极，并且第二写入晶体管耦合到第二反相器的输出，并且具有耦合到所述源的第二组写控制信号。最后，传输晶体管具有耦合到第一和第二反相器的输出的栅极。

62. 发明授权

US07495473B2 Non-volatile look-up table for an FPGA 有权
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07495473B2
公开(公告)日：2009-02-24
申请号：US11858330
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。多路复用器具有x地址输入，其中2x = n，如本领域已知的。多路复用器的输出通过上拉晶体管耦合到Vcc。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

63. 发明申请

US20080191363A1 ARCHITECTURE FOR FACE-TO-FACE BONDING BETWEEN SUBSTRATE AND MULTIPLE DAUGHTER CHIPS 审中-公开
标题翻译：基板和多个钻头之间的面对面结合的结构
公开(公告)号：US20080191363A1
公开(公告)日：2008-08-14
申请号：US12102765
申请日：2008-04-14
申请人： William C. Plants , John McCollum , Theodore Speers
发明人： William C. Plants , John McCollum , Theodore Speers
IPC分类号： H01L23/48
CPC分类号： H01L25/18 , H01L24/06 , H01L2224/0554 , H01L2224/05573 , H01L2224/06136 , H01L2224/16145 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H03K19/17732 , H03K19/17744 , H03K19/17796 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit system includes a first integrated circuit die and a family of second integrated circuit dice. The first integrated circuit die have input/output circuits disposed thereon and further have a first array of face-to-face bonding structures disposed on a first face thereof. Each member of the family of second integrated circuit dice have logical function circuits disposed thereon and further have a second array of face-to-face bonding structures disposed on a first face thereof. The second array of face-to-face bonding structures of each member of the family mates with a different portion of the first array of face-to-face bonding structures.
摘要翻译：集成电路系统包括第一集成电路管芯和第二集成电路管芯系列。第一集成电路管芯具有设置在其上的输入/输出电路，并且还具有设置在其第一面上的面对面结合结构的第一阵列。第二集成电路骰子族的每个成员具有设置在其上的逻辑功能电路，并且还具有设置在其第一面上的面对面结合结构的第二阵列。该系列的每个构件的面对面结合结构的第二阵列与第一阵列的面对面结合结构的不同部分相配合。

64. 发明申请

US20080122481A1 PROGRAMMABLE SYSTEM ON A CHIP 有权
公开(公告)号：US20080122481A1
公开(公告)日：2008-05-29
申请号：US11932462
申请日：2007-10-31
申请人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William C. Plants
发明人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William C. Plants
IPC分类号： G06F7/38
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

65. 发明授权

US07126374B2 Multi-level routing architecture in a field programmable gate array having transmitters and receivers 失效
标题翻译：具有发射机和接收机的现场可编程门阵列中的多级路由架构
公开(公告)号：US07126374B2
公开(公告)日：2006-10-24
申请号：US11074922
申请日：2005-03-07
申请人： Arunangshu Kundu , Venkatesh Narayanan , John McCollum , William C. Plants
发明人： Arunangshu Kundu , Venkatesh Narayanan , John McCollum , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.
摘要翻译：具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构组件。

66. 发明申请

US20050237083A1 Programmable system on a chip 有权
标题翻译：可编程系统芯片
公开(公告)号：US20050237083A1
公开(公告)日：2005-10-27
申请号：US10843701
申请日：2004-05-10
申请人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William Plants
发明人： Greg Bakker , Khaled El-Ayat , Theodore Speers , Limin Zhu , Brian Schubert , Rabindranath Balasubramanian , Kurt Kolkind , Thomas Barraza , Venkatesh Narayanan , John McCollum , William Plants
IPC分类号： H01L20060101 , H03K19/177
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
摘要翻译：一种可编程片上系统集成电路装置，包括可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块。可编程互连架构包括可编程元件和互连导体。可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

67. 发明申请

US20050190626A1 Flash/dynamic random access memory field programmable gate array 失效
公开(公告)号：US20050190626A1
公开(公告)日：2005-09-01
申请号：US11113286
申请日：2005-04-21
申请人： John McCollum , Vidya Bellippady , Gregory Bakker
发明人： John McCollum , Vidya Bellippady , Gregory Bakker
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

68. 发明授权

US06891769B2 Flash/dynamic random access memory field programmable gate array 有权
公开(公告)号：US06891769B2
公开(公告)日：2005-05-10
申请号：US10623111
申请日：2003-07-17
申请人： John McCollum , Vidya Bellippady , Gregory Bakker
发明人： John McCollum , Vidya Bellippady , Gregory Bakker
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

69. 发明申请

US20050013186A1 Flash/dynamic random access memory field programmable gate array 有权
标题翻译：闪存/动态随机存取存储器现场可编程门阵列
公开(公告)号：US20050013186A1
公开(公告)日：2005-01-20
申请号：US10623111
申请日：2003-07-17
申请人： John McCollum , Vidya Bellippady , Gregory Bakker
发明人： John McCollum , Vidya Bellippady , Gregory Bakker
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
摘要翻译：用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

70. 发明授权

US06570805B2 Antifuse memory cell and antifuse memory cell array 失效
标题翻译：防漏存储单元和反熔丝存储单元阵列
公开(公告)号：US06570805B2
公开(公告)日：2003-05-27
申请号：US09742550
申请日：2000-12-20
申请人： John McCollum
发明人： John McCollum
IPC分类号： G11C700
CPC分类号： G11C17/16
摘要： An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode of the first antifuse is connected to the first electrode of the second antifuse, and the drain of the MOS transistor is connected to said first electrode of the first antifuse and the first electrode of the second antifuse.
摘要翻译：反熔丝存储单元包括具有第一电极和第二电极的第一反熔丝，具有第一电极和第二电极的第二反熔丝以及具有栅极，源极和漏极的MOS晶体管，其中第一电极反熔丝连接到第二反熔丝的第一电极，并且MOS晶体管的漏极连接到第一反熔丝的第一电极和第二反熔丝的第一电极。

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