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61. 发明申请

US20050027967A1 Apparatus and method for two micro-operation flow using source override 失效
标题翻译：使用源超控的两个微操作流的装置和方法
公开(公告)号：US20050027967A1
公开(公告)日：2005-02-03
申请号：US10631629
申请日：2003-07-30
申请人： Zeev Sperber , Yuval Bustan , Robert Valentine
发明人： Zeev Sperber , Yuval Bustan , Robert Valentine
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.
摘要翻译：一种使用源超控的两个微操作流的方法和装置。在一个实施例中，该方法包括识别具有一个或多个流单个指令多个数据扩展类型操作数的宏指令。一旦接收到，宏指令被解码成第一微操作（uop）和第二uop。一旦被解码，如果第一微操作更新与微操作的逻辑源寄存器匹配的逻辑目标寄存器，则信号被断言以禁用源操作数覆盖逻辑。否则，当在相同的时钟周期中检测到具有匹配逻辑源和目标寄存器的UOP时，互源替代是激活的并由寄存器别名表（RAT）执行。这样，具有128位操作数的宏指令可以在64位实现中使用例如两个uOP（一个用于下半部分，一个用于上半部分）来处理，同时保持原始指令的原子性。

62. 发明申请

US20050027964A1 Apparatus and method for redundant zero micro-operation removal 失效
标题翻译：用于冗余零微操作去除的装置和方法
公开(公告)号：US20050027964A1
公开(公告)日：2005-02-03
申请号：US10631628
申请日：2003-07-30
申请人： Zeev Sperber , Robert Valentine
发明人： Zeev Sperber , Robert Valentine
IPC分类号： G06F9/30 , G06F9/312 , G06F9/318 , G06F15/00
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30043 , G06F9/3016
摘要： A method and apparatus for redundant zero micro-operation removal. In one embodiment, the method includes the identification of a predetermined macro-instruction. Once identified, a value associated with a source register operand of the identified macro-instruction is determined. Once determined, the identified macro-instruction is decoded into a first macro operation and a second micro-operation if the determined value is not set. Otherwise, the identified macro-instruction is decoded into a single micro-operation if the determined value is set. Accordingly, the method described prevents the generation of redundant micro-operations that use valuable resources, such as allocation slots, as well as execution units within the processor core.
摘要翻译：一种用于冗余零微操作移除的方法和装置。在一个实施例中，该方法包括对预定宏指令的识别。一旦确定，确定与所识别的宏指令的源寄存器操作数相关联的值。一旦确定，如果未设置确定的值，则将所识别的宏指令解码为第一宏操作和第二微操作。否则，如果确定的值被设置，则所识别的宏指令被解码为单个微操作。因此，所描述的方法防止了使用诸如分配时隙的有价值的资源以及处理器核心内的执行单元的冗余微操作的产生。

63. 发明授权

US09542154B2 Fused multiply add operations using bit masks 有权
标题翻译：融合乘法使用位掩码添加操作
公开(公告)号：US09542154B2
公开(公告)日：2017-01-10
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/544 , G06F7/76
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

64. 发明授权

US08914430B2 Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions 有权
标题翻译：增加功能单元，能够执行刻度，圆形，GETEXP，圆形，GETMANT，缩小，范围和类指令
公开(公告)号：US08914430B2
公开(公告)日：2014-12-16
申请号：US12890543
申请日：2010-09-24
申请人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
发明人： Amit Gradstein , Cristina S. Anderson , Zeev Sperber , Simon Rubanovich , Benny Eitan
IPC分类号： G06F7/38 , G06F9/38 , G06F9/30
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译：描述了涉及用功能单元执行第一指令的方法。第一条指令是乘法加法指令。该方法还包括执行与功能单元的第二指令。第二个指令是一个圆形指令。

65. 发明申请

US20140189314A1 Real Time Instruction Trace Processors, Methods, and Systems 有权
标题翻译：实时指令跟踪处理器，方法和系统
公开(公告)号：US20140189314A1
公开(公告)日：2014-07-03
申请号：US13730834
申请日：2012-12-29
申请人： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
发明人： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。还公开了其它方法，装置和系统。

66. 发明授权

US08600049B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
公开(公告)号：US08600049B2
公开(公告)日：2013-12-03
申请号：US13506701
申请日：2012-05-10
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

67. 发明申请

US20130227253A1 METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS 审中-公开
公开(公告)号：US20130227253A1
公开(公告)日：2013-08-29
申请号：US13843236
申请日：2013-03-15
申请人： Rajiv Kapoor , Ronen Zohar , Mark J. Buxton , Zeev Sperber , Koby Gottlieb
发明人： Rajiv Kapoor , Ronen Zohar , Mark J. Buxton , Zeev Sperber , Koby Gottlieb
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

68. 发明申请

US20130166884A1 METHOD AND APPARATUS FOR PERFORMING LOGICAL COMPARE OPERATIONS 审中-公开
公开(公告)号：US20130166884A1
公开(公告)日：2013-06-27
申请号：US13763598
申请日：2013-02-08
申请人： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
发明人： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

69. 发明申请

US20120224687A1 Method and apparatus for optimizing Advanced Encryption Standard (AES) encryption and decryption in parallel modes of operation 有权
标题翻译：用于在并行运行模式下优化高级加密标准（AES）加密和解密的方法和装置
公开(公告)号：US20120224687A1
公开(公告)日：2012-09-06
申请号：US13506701
申请日：2012-05-10
申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
发明人： Shay Gueron , Amit Gradstein , Zeev Sperber
IPC分类号： G06F21/24
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
摘要翻译：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

70. 发明授权

US08103858B2 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US08103858B2
公开(公告)日：2012-01-24
申请号：US12217084
申请日：2008-06-30
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

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