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    • 63. 发明授权
    • Multiprocessor system using stacked processor modules and board to board connectors
    • 使用堆叠处理器模块和板对板连接器的多处理器系统
    • US07606959B2
    • 2009-10-20
    • US11606307
    • 2006-11-27
    • Li YaoWei Chen
    • Li YaoWei Chen
    • G06F13/00
    • G06F15/17
    • A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor modules and the baseboard; the processors communicate with the peripheral equipments in accordance with a specific bus specification; and the operations of the plurality of processor modules are coordinated by routes provided between the processor modules and between the processor modules and the baseboard.
    • 提供一种多处理器系统,包括用于布置外围设备的基板; 以及多个处理器模块,每个处理器模块配备有处理器和板对板连接器; 其中所述多个处理器模块被堆叠起来,其中板对板连接器电连接在所述处理器模块之间以及所述处理器模块和所述基板之间; 处理器根据特定总线规格与周边设备进行通信; 并且多个处理器模块的操作由设置在处理器模块之间以及处理器模块和基板之间的路由进行协调。
    • 65. 发明授权
    • Method of displaying multi-channel waveforms
    • 显示多通道波形的方法
    • US07260489B2
    • 2007-08-21
    • US11316182
    • 2005-12-22
    • Li YaoWei Chen
    • Li YaoWei Chen
    • G01R13/02
    • G16H40/63G06F19/00
    • A method of displaying multi-channel waveforms including the steps of: dividing at least one waveform screen in a video memory which is mapped to a display terminal into a plurality of waveform windows, wherein boundaries of each of the windows are defined by a plurality of values set in at least a set of boundary registers; establishing a waveform parameter table in a system memory; writing waveform data into a logical space in the waveform screen corresponding to a waveform by writing operations from CPU to the video memory; and based on parameters of the waveform windows in the waveform parameter table, performing a display mode defined by the parameter by means of changing the mapping relationship between the video memory and the display terminal, before transmitting the data of each of the waveform windows read out from the video memory to the display terminal.
    • 一种显示多声道波形的方法,包括以下步骤:将映射到显示终端的视频存储器中的至少一个波形屏幕划分成多个波形窗口,其中每个窗口的边界由多个 至少在一组边界寄存器中设置值; 在系统存储器中建立波形参数表; 通过将操作从CPU写入视频存储器,将波形数据写入与波形对应的波形画面中的逻辑空间; 并且基于波形参数表中的波形窗口的参数,在发送读出的每个波形窗口的数据之前,通过改变视频存储器和显示终端之间的映射关系来执行由该参数定义的显示模式 从视频存储器到显示终端。
    • 66. 发明申请
    • Method and apparatus for accelerating the display of horizontal lines
    • 用于加速水平线显示的方法和装置
    • US20060119604A1
    • 2006-06-08
    • US11293349
    • 2005-12-02
    • Li YaoWei Chen
    • Li YaoWei Chen
    • G09G5/39
    • G09G5/363
    • The present invention relates to a method and apparatus for accelerating the display of horizontal lines used in an embedded system. The embedded system comprising a CPU (Central Processing Unit), a display terminal, a video memory for storing one or more display data, each data corresponds to a respective pixel on the display terminal, and a display-driving circuit for generating logic signals to read the display data from the video memory and delivering the display data to the display terminal for display, the apparatus for accelerating the display of horizontal lines comprising: a video memory controller, coupled to the CPU, the display-driving circuit and the video memory, for receiving from the CPU all request signals for performing reading and writing operations with the video memory, generating respective logic signals in response to the request signals and controlling the operations of reading data from or writing data into the video memory; a FIFO (First-In First-Out) buffer, coupled to a CPU bus, for, when the CPU provides an instruction for performing an operation of writing data into the video memory, buffering a control word sent by the CPU to the video memory controller, and the starting address for writing data into the video memory and the data to be written; and a line-accelerating register, comprising a length register for registering a line length value from the CPU and a line-accelerating flag for indicating an instruction for displaying a point or displaying a line from the CPU, wherein the FIFO buffer is also coupled to the output of the line-accelerating register and the FIFO buffer outputs a signal indicating whether it's empty or not to the video memory controller.
    • 本发明涉及加速在嵌入式系统中使用的水平线的显示的方法和装置。 嵌入式系统包括CPU(中央处理单元),显示终端,用于存储一个或多个显示数据的视频存储器,每个数据对应于显示终端上的相应像素,以及显示驱动电路,用于产生逻辑信号 从视频存储器读取显示数据并将显示数据传送到显示终端进行显示,用于加速水平线的显示的装置包括:视频存储器控制器,耦合到CPU,显示驱动电路和视频存储器 用于从CPU接收所有请求信号以执行与视频存储器的读和写操作,响应于请求信号产生相应的逻辑信号,并控制从数据读取数据或将数据写入视频存储器的操作; 一个FIFO(先进先出)缓冲器,耦合到CPU总线,用于当CPU提供用于执行将数据写入视频存储器的操作的指令时,将由CPU发送的控制字缓冲到视频存储器 控制器和将数据写入视频存储器的起始地址和要写入的数据; 以及线加速寄存器,包括用于从CPU注册线路长度值的长度寄存器和用于指示用于显示点或从CPU显示线路的指令的线路加速标志,其中FIFO缓冲器还耦合到 线路加速寄存器和FIFO缓冲器的输出向视频存储器控制器输出指示是否为空的信号。