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61. 发明申请

US20050280132A1 Semiconductor package with heat sink 有权
标题翻译：半导体封装带散热片
公开(公告)号：US20050280132A1
公开(公告)日：2005-12-22
申请号：US11212290
申请日：2005-08-26
申请人： Chang-Fu Lin , Han-Ping Pu , Cheng-Hsu Hsiao , Chien Huang
发明人： Chang-Fu Lin , Han-Ping Pu , Cheng-Hsu Hsiao , Chien Huang
IPC分类号： H01L23/367 , H01L23/06
CPC分类号： H01L23/36 , H01L23/3675 , H01L23/49816 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16315 , H01L2924/19105 , H01L2924/00014
摘要： A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.
摘要翻译：提供了具有散热器的半导体封装，其中至少一个芯片安装在基板上并被散热器覆盖。散热器在与基板接触的位置处形成有多个凹槽或孔，允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。因此，不需要在基板上形成预定的孔，用于连接诸如螺栓的固定构件，并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置不会导致芯片的裂纹。

62. 发明申请

US20050168952A1 Semiconductor package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20050168952A1
公开(公告)日：2005-08-04
申请号：US10974513
申请日：2004-10-26
申请人： Chin-Te Chen , Han-Ping Pu
发明人： Chin-Te Chen , Han-Ping Pu
IPC分类号： H01L23/04 , H01L23/10 , H05K7/20
CPC分类号： H01L23/04 , H01L23/10 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16315
摘要： A semiconductor package includes a substrate; a chip mounted on a surface of the substrate; a lid having a flat portion and a support portion extending from the flat portion, wherein the support portion is attached to the substrate, with the chip being encompassed by the flat portion, the support portion and the substrate, and at least one cut-away portion is formed at an outer edge of a surface of the support portion attached to the substrate; an adhesive for attaching the lid to the substrate and filling the cut-away portion to allow an applied amount of the adhesive to be observed from the cut-away portion; and a plurality of solder balls mounted on another surface of the substrate. The applied amount of the adhesive can be adjusted optimally by provision of the cut-away portion to improve bonding strength between the lid and substrate and prevent flash of the adhesive.
摘要翻译：半导体封装包括基板; 安装在基板的表面上的芯片; 具有平坦部分和从所述平坦部分延伸的支撑部分的盖，其中所述支撑部分附接到所述基板，所述芯片被所述平坦部分，所述支撑部分和所述基板包围，并且至少一个切除部分形成在附着于基板的支撑部分的表面的外边缘处; 粘合剂，用于将盖子附接到基板并填充切除部分，以允许从切除部分观察涂布量的粘合剂; 以及安装在所述基板的另一表面上的多个焊球。可以通过设置切除部分来最佳地调节粘合剂的施加量，以提高盖和基板之间的粘合强度并防止粘合剂的闪光。

63. 发明授权

US06891273B2 Semiconductor package and fabrication method thereof 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US06891273B2
公开(公告)日：2005-05-10
申请号：US10404173
申请日：2003-04-01
申请人： Han-Ping Pu , Chien Ping Huang
发明人： Han-Ping Pu , Chien Ping Huang
IPC分类号： H01L21/60 , H01L23/31 , H01L23/538 , H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/16 , H01L2224/24011 , H01L2224/24226 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/3025 , H01L2224/82 , H01L2924/00 , H01L2224/05647 , H01L2924/00014 , H01L2224/05655 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171
摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.
摘要翻译：提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

64. 发明申请

US20050036291A1 Semiconductor package with heat dissipating structure 有权
标题翻译：具有散热结构的半导体封装
公开(公告)号：US20050036291A1
公开(公告)日：2005-02-17
申请号：US10759863
申请日：2004-01-16
申请人： Chien-Ping Huang , Han-Ping Pu , Chin-Te Chen , Chang-Fu Lin
发明人： Chien-Ping Huang , Han-Ping Pu , Chin-Te Chen , Chang-Fu Lin
IPC分类号： H01L21/48 , H01L21/56 , H01L23/055 , H01L23/10 , H01L23/367 , H01L23/467 , H01L25/065 , H05K7/20
CPC分类号： H01L23/467 , H01L21/4882 , H01L21/563 , H01L23/055 , H01L23/10 , H01L23/3672 , H01L23/3675 , H01L25/0655 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/16315 , H01L2924/19105 , H01L2924/3011 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor package with a heat dissipating structure includes a substrate, a chip and a heat dissipating structure. The chip is mounted on and electrically connected to the substrate. The heat dissipating structure includes a first heat sink having at least one positioning portion, and at least one second heat sink having at least one second positioning portion and at least one hollow portion. The second heat sink is mounted on the substrate, and the first positioning portion of the first heat sink is attached to the second positioning portion of the second heat sink, allowing the chip to be accommodated in a space defined by the first heat sink, the hollow portion of the second heat sink and the substrate. This semiconductor package has good heat dissipating efficiency and is cost-effective to fabricate.
摘要翻译：具有散热结构的半导体封装包括基板，芯片和散热结构。芯片安装在基板上并电连接到基板。散热结构包括具有至少一个定位部分的第一散热器和具有至少一个第二定位部分和至少一个中空部分的至少一个第二散热器。第二散热器安装在基板上，并且第一散热器的第一定位部分附接到第二散热器的第二定位部分，允许芯片容纳在由第一散热器限定的空间中，第二散热器的中空部分和基板。该半导体封装具有良好的散热效率，并且制造成本低。

65. 发明授权

US06593662B1 Stacked-die package structure 有权
标题翻译：堆叠式封装结构
公开(公告)号：US06593662B1
公开(公告)日：2003-07-15
申请号：US09631343
申请日：2000-08-02
申请人： Han-Ping Pu , Randy H. Y. Lo , Tzong-Dar Her , Chien-Ping Huang , Cheng-Shiu Hsiao , Chi-Chuan Wu
发明人： Han-Ping Pu , Randy H. Y. Lo , Tzong-Dar Her , Chien-Ping Huang , Cheng-Shiu Hsiao , Chi-Chuan Wu
IPC分类号： H01L2348
CPC分类号： H01L24/33 , H01L23/4334 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2224/83194 , H01L2224/8385 , H01L2224/85399 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.
摘要翻译：堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。载体具有与上表面相对的上表面和后表面。基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。间隔件位于两个相邻的模具之间。位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。导体线分别电连接在管芯和载体的每个接合焊盘之间。并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。具有焊球或具有引脚的引线框架的基板适合用作载体。

66. 发明授权

US06469897B2 Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same 失效
公开(公告)号：US06469897B2
公开(公告)日：2002-10-22
申请号：US09774211
申请日：2001-01-30
申请人： Tzong-Da Ho , Chien-Ping Huang , Han-Ping Pu
发明人： Tzong-Da Ho , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H05K720
CPC分类号： H01L23/49816 , H01L23/36 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , Y10T29/4935 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad. The proposed TBGA technology allows the resulted grounding plug to be firmly secured in position due to the filled solder being wettable to the heat sink, thereby providing a greater ball shear strength to the grounding solder ball that is subsequently bonded to the grounding plug. The finished TBGA package would be therefore assured in the reliability of its grounding structure.

67. 发明授权

US06400036B1 Flip-chip package structure and method of fabricating the same 有权
标题翻译：倒装芯片封装结构及其制造方法
公开(公告)号：US06400036B1
公开(公告)日：2002-06-04
申请号：US09920069
申请日：2001-08-01
申请人： Wei-Sen Tang , Han-Ping Pu
发明人： Wei-Sen Tang , Han-Ping Pu
IPC分类号： H01L2144
CPC分类号： H01L24/32 , H01L21/563 , H01L24/28 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/26145 , H01L2224/26175 , H01L2224/27013 , H01L2224/32145 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.
摘要翻译：提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料在从闪烁到其他非预期区域的倒装芯片底部填充过程中。闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和可靠性。

68. 发明授权

US09064881B2 Protecting flip-chip package using pre-applied fillet 有权
标题翻译：使用预应用的圆角保护倒装芯片封装
公开(公告)号：US09064881B2
公开(公告)日：2015-06-23
申请号：US12944453
申请日：2010-11-11
申请人： Tsung-Fu Tsai , Yian-Liang Kuo , Ming-Song Sheu , Yu-Ling Tsai , Chen-Shien Chen , Han-Ping Pu
发明人： Tsung-Fu Tsai , Yian-Liang Kuo , Ming-Song Sheu , Yu-Ling Tsai , Chen-Shien Chen , Han-Ping Pu
IPC分类号： H01L23/29 , H01L21/56 , H01L23/00
CPC分类号： H01L21/78 , H01L21/02013 , H01L21/02016 , H01L21/563 , H01L23/295 , H01L23/562 , H01L24/32 , H01L24/743 , H01L24/81 , H01L2224/16225 , H01L2224/26145 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/81009 , H01L2224/81191 , H01L2224/83104 , H01L2224/83192 , H01L2224/92125 , H01L2924/10156 , H01L2924/14 , H01L2924/00012 , H01L2924/10155 , H01L2924/00
摘要： A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.
摘要翻译：模具具有第一表面，与第一表面相对的第二表面，并且侧壁包括第一部分和第二部分，其中第一部分比第二部分更靠近第一表面。圆角接触模具的侧壁的第一部分并且环绕模具。工件通过焊料凸块与模具结合，第二表面面向工件。第一底部填充物填充模具和工件之间的间隙，其中第一底部填充物接触圆角，并且其中第一底部填充物和圆角由不同的材料形成。

69. 发明授权

US08927333B2 Die carrier for package on package assembly 有权
标题翻译：封装组件上的封装的载体
公开(公告)号：US08927333B2
公开(公告)日：2015-01-06
申请号：US13302059
申请日：2011-11-22
申请人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
发明人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
IPC分类号： H01L21/00 , H01L21/76 , H01L23/48 , H01L23/552 , H01L25/10
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/1017 , H01L2225/1041 , H01L2225/1058 , H01L2924/00012
摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.
摘要翻译：提供了一种用于在回流操作期间维持管芯对准的封装封装布置。第一顶模具有焊料凸块的第一布置。底部封装具有电连接到第一焊料凸点布置的第一电气布置。模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

70. 发明授权

US08759964B2 Wafer level package structure and fabrication methods 有权
标题翻译：晶圆级封装结构及制作方法
公开(公告)号：US08759964B2
公开(公告)日：2014-06-24
申请号：US11779192
申请日：2007-07-17
申请人： Han-Ping Pu , Mirng-Ji Lii
发明人： Han-Ping Pu , Mirng-Ji Lii
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L23/3107 , H01L24/13 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/20 , H01L2224/97 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/82 , H01L2224/29099 , H01L2924/00
摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.
摘要翻译：提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

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