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61. 发明申请

US20120032318A1 LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：层状芯片包装及其制造方法
公开(公告)号：US20120032318A1
公开(公告)日：2012-02-09
申请号：US12852767
申请日：2010-08-09
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
IPC分类号： H01L25/11 , H01L21/98 , H01L25/07
CPC分类号： H01L25/50 , H01L23/5382 , H01L24/01 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2924/07802 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.
摘要翻译：分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。主体包括：主要部分，包括多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。每个层部分包括半导体芯片。多个第二端子被定位成在垂直于主体顶表面的方向上与多个第一端子重叠。经由导线电连接的多对第一和第二端子包括定位为不彼此重叠的多对第一端子和第二端子。

62. 发明申请

US20110242703A1 Thermally assisted magnetic head, method of manufacturing the same, head gimbal assembly, and hard disk drive 有权
标题翻译：热辅助磁头，制造方法，磁头万向节组件和硬盘驱动器
公开(公告)号：US20110242703A1
公开(公告)日：2011-10-06
申请号：US12662138
申请日：2010-03-31
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hironori Araki , Shigeki Tanemura , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Hironori Araki , Shigeki Tanemura , Atsushi Iijima
IPC分类号： G11B5/48 , G11B5/187 , B05D5/12
CPC分类号： G11B5/6005 , G02B6/122 , G11B5/3116 , G11B5/314 , G11B5/3163 , G11B5/6088 , G11B2005/0021
摘要： A thermally assisted magnetic head includes a main magnetic pole layer, a near-field light generating layer having a generating end part generating near-field light arranged within a medium-opposing surface, and an optical waveguide guiding light to the near-field light generating layer. The thermally assisted magnetic head includes a base layer which a base groove part having a width gradually getting smaller along a depth direction and extending in an intersecting direction intersecting with the medium-opposing surface is formed. The near-field light generating layer has an in-groove generating layer formed inside of the base groove part. The in-groove generating layer is formed along an inner wall surface of the base groove part and has a thin-film like structure.
摘要翻译：一种热辅助磁头包括主磁极层，具有产生在介质相对表面内布置的近场光的产生端部分的近场光产生层和将光引导到近场光产生层。热辅助磁头包括基底层，基底槽部分的宽度随着深度方向逐渐变小并且在与介质相对表面相交的相交方向上延伸。近场光产生层具有形成在基槽部内的内槽生成层。槽内产生层沿着基部槽部的内壁面形成，具有薄膜状结构。

63. 发明申请

US20110228418A1 HEAT-ASSISTED MAGNETIC RECORDING HEAD WITH NEAR-FIELD LIGHT GENERATING ELEMENT 有权
标题翻译：具有近场光产生元件的热辅助磁记录头
公开(公告)号：US20110228418A1
公开(公告)日：2011-09-22
申请号：US12727666
申请日：2010-03-19
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Shigeki Tanemura , Hironori Araki , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Shigeki Tanemura , Hironori Araki , Atsushi Iijima
IPC分类号： G11B5/02
CPC分类号： G11B5/314 , G11B5/3163 , G11B5/6088 , G11B2005/001 , G11B2005/0021
摘要： A near-field light generating element has an outer surface including a bottom surface that lies at an end closer to a top surface of a substrate, a waveguide facing surface that lies at an end farther from the top surface of the substrate and faces a waveguide, a front end face located in a medium facing surface, and a side surface that connects the bottom surface, the waveguide facing surface and the front end face to each other. The front end face includes a first side that lies at an end of the bottom surface, a tip that lies at an end farther from the top surface of the substrate and forms a near-field light generating part, a second side that connects an end of the first side to the tip, and a third side that connects the other end of the first side to the tip. The waveguide facing surface includes a width changing portion that has a width in a direction parallel to the bottom surface and the front end face, the width decreasing with decreasing distance to the front end face.
摘要翻译：近场光产生元件具有外表面，该外表面包括位于更靠近基板顶表面的一端的底表面，位于远离基板顶表面的一端的波导对面的表面，位于介质相对表面中的前端面以及将所述底表面，所述波导对向表面和所述前端面彼此连接的侧表面。所述前端面包括位于所述底面的端部的第一侧，位于距离所述基板的上表面更远的一端并形成近场光产生部的端部，所述第二侧将端部并且将第一侧的另一端连接到尖端的第三侧。面向波导的表面包括宽度改变部分，该宽度改变部分在平行于底面和前端面的方向上具有宽度，宽度随着与前端面的距离的减小而减小。

64. 发明申请

US20110228416A1 A METHOD OF MANUFACTURING A THERMALLY ASSISTED MAGNETIC HEAD 有权
标题翻译：制造热辅助磁头的方法
公开(公告)号：US20110228416A1
公开(公告)日：2011-09-22
申请号：US12659691
申请日：2010-03-17
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
IPC分类号： G11B21/16 , H01F7/06
CPC分类号： G11B5/3163 , B82Y20/00 , G02B6/1226 , G11B5/105 , G11B5/314 , G11B5/6088 , G11B2005/0021 , Y10T29/49021 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49052
摘要： A thermally assisted magnetic head is formed by performing a head forming process, a mounting part forming process and a light source mounting process in that order. In the head forming process, a planned area is secured on a light source placing surface of a slider substrate, then a magnetic head part is formed on a head area other than the planned area and a spacer for securing a mounting space for the laser diode is formed on the planned area. In the mounting part forming process, a light source mounting part is formed by removing the spacer. In the light source mounting process, a laser diode is mounted on the light source mounting part formed by the mounting part forming step.
摘要翻译：通过以该顺序执行头部成形工艺，安装部件形成工艺和光源安装工艺来形成热辅助磁头。在头部成形处理中，将规划区域固定在滑块基板的光源放置面上，然后将磁头部形成在除了规划区域以外的头部区域上，并且用于固定激光二极管的安装空间的间隔件在规划区域形成。在安装部形成工序中，通过移除间隔件形成光源安装部。在光源安装过程中，激光二极管安装在由安装部分形成步骤形成的光源安装部分上。

65. 发明申请

US20110068456A1 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US20110068456A1
公开(公告)日：2011-03-24
申请号：US12585778
申请日：2009-09-24
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
IPC分类号： H01L25/065 , H01L21/50 , H01L21/66
CPC分类号： H01L24/94 , H01L23/481 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/1147 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2224/05552
摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.
摘要翻译：分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。

66. 发明授权

US07902677B1 Composite layered chip package and method of manufacturing same 有权
标题翻译：复合分层芯片封装及其制造方法
公开(公告)号：US07902677B1
公开(公告)日：2011-03-08
申请号：US12588808
申请日：2009-10-28
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
IPC分类号： H01L23/48 , H01L23/29 , H01L23/28
CPC分类号： H01L24/96 , H01L21/6835 , H01L23/3171 , H01L24/06 , H01L24/16 , H01L24/25 , H01L24/29 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/05553 , H01L2224/05647 , H01L2224/12105 , H01L2224/13099 , H01L2224/32145 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2225/06513 , H01L2225/06551 , H01L2225/1035 , H01L2225/1064 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/18162 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.
摘要翻译：复合分层芯片封装包括堆叠的多个子封装。每个子包包括主体和布置在主体的侧表面上的布线。主体具有包括至少一个第一类型层部分的主要部分。对于任何两个垂直相邻的子包装，下部子包装的主体具有布置在主要部件的顶表面上的多个第一端子，而上部子包装的主体具有多个第二端子，第二端子布置在主要部分的底面。多个子包中的至少一个子包的主体的主要部分包括至少一个第二类型层部分。第一型层部分包括一致的半导体芯片，而第二型层部分包括有缺陷的半导体芯片。

67. 发明授权

US08652877B2 Method of manufacturing layered chip package 有权
标题翻译：分层芯片封装的制造方法
公开(公告)号：US08652877B2
公开(公告)日：2014-02-18
申请号：US12960921
申请日：2010-12-06
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Hiroshi Ikejima , Atsushi Iijima
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L23/49805 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/24137 , H01L2225/06513 , H01L2225/06551 , H01L2225/06565 , H01L2924/07802 , H01L2924/18162 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.
摘要翻译：分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。主体包括多个堆叠层部分。制造层状芯片封装的方法包括制造层状子结构的步骤和切割层状子结构的步骤。分层子结构包括：多个排列的预分离主体; 设置在两个相邻的预分离主体之间的多个容纳部件; 以及容纳在容纳部中的多条初级线。通过光刻在光敏树脂层中形成住宿部。在切割层状子结构的步骤中，多个预分离主体彼此分离，并且通过初步线形成电线。

68. 发明授权

US08455349B2 Layered chip package and method of manufacturing same 有权
标题翻译：分层芯片封装及其制造方法
公开(公告)号：US08455349B2
公开(公告)日：2013-06-04
申请号：US12769361
申请日：2010-04-28
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima , Tatsuya Harada
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L22/22 , H01L23/3121 , H01L23/481 , H01L24/05 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/04105 , H01L2224/05551 , H01L2224/05554 , H01L2224/24146 , H01L2224/32145 , H01L2224/73267 , H01L2224/82005 , H01L2224/82101 , H01L2224/83005 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/1453 , H01L2924/181 , H01L2224/03 , H01L2924/00
摘要： A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.
摘要翻译：分层芯片封装包括主体和多个贯通电极。主体包括层叠的多个层部分和穿透所有多个层部分的多个通孔。多个贯通电极设置在主体的多个通孔中，并穿透所有多个层部分。多个层部分中的每一个包括半导体芯片。多个层部分中的至少一个包括将半导体芯片电连接到多个贯通电极的布线。布线包括多个导体，其与暴露在多个通孔中的任一个的壁面中的穿通电极接触并穿过通孔。

69. 发明授权

US08426947B2 Laminated semiconductor wafer, laminated chip package and method of manufacturing the same 有权
标题翻译：层叠半导体晶片，层压芯片封装及其制造方法
公开(公告)号：US08426947B2
公开(公告)日：2013-04-23
申请号：US12848569
申请日：2010-08-02
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
IPC分类号： H01L23/544
CPC分类号： H01L23/552 , H01L21/561 , H01L21/6835 , H01L23/3114 , H01L23/3178 , H01L24/05 , H01L24/32 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/02166 , H01L2224/04042 , H01L2224/04105 , H01L2224/05553 , H01L2224/05554 , H01L2224/05568 , H01L2224/05647 , H01L2224/32145 , H01L2224/48463 , H01L2224/83005 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06551 , H01L2225/06565 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , H01L2924/3025 , H01L2224/03 , H01L2924/00
摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.
摘要翻译：在层叠半导体衬底中层叠多个半导体衬底。每个半导体衬底具有沿着划线形成的多个划线槽部分。此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件。此外，最上面的基板和最下面的基板具有使用铁磁体形成的电磁屏蔽层。电磁屏蔽层形成在除延伸区域之外的屏蔽区域中。延伸区设置为布线电极在器件区域的周边部分中交叉的部分。

70. 发明授权

US08426946B2 Laminated semiconductor substrate, laminated chip package and method of manufacturing the same 有权
标题翻译：层叠半导体衬底，层压芯片封装及其制造方法
公开(公告)号：US08426946B2
公开(公告)日：2013-04-23
申请号：US12801837
申请日：2010-06-28
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/563 , H01L21/6835 , H01L23/522 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/25 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/03444 , H01L2224/0345 , H01L2224/0346 , H01L2224/0392 , H01L2224/04026 , H01L2224/05008 , H01L2224/05644 , H01L2224/05647 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2919 , H01L2224/32145 , H01L2224/32148 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/83121 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/95001 , H01L2224/97 , H01L2225/06565 , H01L2924/01029 , H01L2924/07802 , H01L2924/14 , H01L2924/00
摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.
摘要翻译：在层叠半导体衬底中层叠多个半导体衬底。每个半导体衬底具有沿着划线形成的多个划线槽部分。此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件，第一布线电极和第二布线电极从第一器件区域延伸到插入的沟槽部分的内部，并且第二装置区域，并且彼此分离。在层叠半导体基板中，形成有第一配线电极的通孔。层叠半导体基板具有贯通电极。通孔与通孔中出现的所有第一布线电极接触。层叠半导体衬底具有多个层叠芯片区域。

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