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    • 68. 发明授权
    • Method and apparatus for image forming capable of effectively transporting toner
    • 能够有效地输送调色剂的成像方法和装置
    • US07315723B2
    • 2008-01-01
    • US11125177
    • 2005-05-10
    • Takeo SudaShinichi KawaharaKeiichi YoshidaYoshio HattoriYutaka Takahashi
    • Takeo SudaShinichi KawaharaKeiichi YoshidaYoshio HattoriYutaka Takahashi
    • G03G21/00
    • G03G21/105G03G2221/0005G03G2221/1624
    • An image forming apparatus includes a photoconductor, a cleaning device, and a toner transporting device. The photoconductor has a toner image formed thereon. The cleaning device removes toner remaining on the photoconductor. The toner transporting device transports the toner removed by the cleaning device. The toner transporting device includes a first toner transport path forming member, a first toner transporting member, and a length control member. The first toner transporting member is partly provided in the first toner transport path forming member, expands and contracts in a length direction thereof, and transports the toner through the first toner transport path forming member. The length control member is provided at a downstream end of the first toner transport path forming member, and is pressed against the first toner transporting member to keep a constant length of the first toner transporting member. An image forming method is also described.
    • 图像形成装置包括光电导体,清洁装置和调色剂输送装置。 光电导体具有形成在其上的调色剂图像。 清洁装置去除光电导体上残留的调色剂。 调色剂输送装置输送由清洁装置去除的调色剂。 调色剂输送装置包括第一调色剂输送路径形成部件,第一调色剂输送部件和长度控制部件。 第一调色剂输送构件部分地设置在第一调色剂输送路径形成构件中,在其长度方向上膨胀和收缩,并且通过第一调色剂输送路径形成构件输送调色剂。 长度控制构件设置在第一调色剂输送路径形成构件的下游端,并且被压靠第一调色剂输送构件以保持第一调色剂输送构件的恒定长度。 还描述了一种图像形成方法。
    • 70. 发明申请
    • Nonvolatile semiconductor storage device
    • 非易失性半导体存储器件
    • US20050157548A1
    • 2005-07-21
    • US10503619
    • 2002-02-28
    • Tsutomu NakajimaKeiichi Yoshida
    • Tsutomu NakajimaKeiichi Yoshida
    • G11C11/56G11C16/26G11C16/04
    • G11C11/412G11C11/5642G11C16/26
    • A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.
    • 基于用于存储两个或更多位的信息的多级存储技术的闪速存储器1具有四个存储体2a至2d。 例如,在存储体2a的左侧,沿着存储体2a的一个短边设置数据锁存器6a,而在右侧,沿着另一个短边设置数据锁存器6b, 银行2 a。 在数据锁存器6a,6b的下侧设有运算电路7a,7b。 数据锁存器6a,6b分别由SRAM形成。 感测锁定器5a相对于感测闩锁行的中心在左右方向上被分成一半。 划分的检测锁存器5a通过分别沿着存储体2a的两个短边分配的信号线与数据锁存器6a,6b连接。