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61. 发明授权

US08225058B2 Memory system managing a size of logs 有权
标题翻译：管理日志大小的内存系统
公开(公告)号：US08225058B2
公开(公告)日：2012-07-17
申请号：US12559983
申请日：2009-09-15
申请人： Hironobu Miyamoto , Hajime Yamazaki , Shinji Yonezawa
发明人： Hironobu Miyamoto , Hajime Yamazaki , Shinji Yonezawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1471 , G06F2201/84 , G06F2212/7201
摘要： A memory system according to an embodiment of the present invention includes: a log overflow control unit configured, when a predetermined condition is satisfied, to prohibit a recording operation of a log and to cause a log recording unit only to perform an updating operation of a management table, and when a commit condition is satisfied after the predetermined condition has been satisfied, to prohibit a commit operation by a log reflecting unit and to cause a snapshot storing unit to perform a snapshot storing operation.
摘要翻译：根据本发明的实施例的存储器系统包括：日志溢出控制单元，当满足预定条件时，配置为禁止日志的记录操作，并且使日志记录单元仅执行日志记录单元的更新操作管理表，并且在满足预定条件之后满足提交条件时，禁止日志反射单元的提交操作，并使快照存储单元执行快照存储操作。

62. 发明授权

US08198652B2 Field effect transistor with reduced gate leakage current 有权
标题翻译：具有减小栅极漏电流的场效应晶体管
公开(公告)号：US08198652B2
公开(公告)日：2012-06-12
申请号：US12295004
申请日：2007-03-29
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

63. 发明申请

US20110278586A1 BIPOLAR TRANSISTOR 有权
标题翻译：双极晶体管
公开(公告)号：US20110278586A1
公开(公告)日：2011-11-17
申请号：US13124873
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/20
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66318
摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0
摘要翻译：双极晶体管设置有发射极层，基极层和集电极层。发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。集电极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

64. 发明申请

US20100276732A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100276732A1
公开(公告)日：2010-11-04
申请号：US12810096
申请日：2008-12-25
申请人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
发明人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
IPC分类号： H01L29/78
CPC分类号： H01L29/66462 , H01L27/0605 , H01L29/0891 , H01L29/2003 , H01L29/4232 , H01L29/7781
摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.
摘要翻译：半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

65. 发明申请

US20100230684A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100230684A1
公开(公告)日：2010-09-16
申请号：US12299542
申请日：2007-05-07
申请人： Yasuhiro Okamoto , Yuji Ando , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
发明人： Yasuhiro Okamoto , Yuji Ando , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
IPC分类号： H01L29/80 , H01L29/205
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316
摘要： A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0≦y≦1, 0≦z≦1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.
摘要翻译：半导体器件包括沟道层，设置在沟道层上的电子供给层，设置在电子供给层上并与沟道层形成晶格匹配的盖层以及设置在盖层上的欧姆电极。盖层具有（InyAl1-y）zGa1-zN（0＆nlE; y＆nlE; 1,0＆amp; nlE; z＆nlE; 1）的组成。这种盖层的z随着远离电子供应层而单调减小。

66. 发明申请

US20100038680A1 III-NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译： III-NITRIDE半导体场效应晶体管
公开(公告)号：US20100038680A1
公开(公告)日：2010-02-18
申请号：US12528578
申请日：2008-02-26
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Takashi Inoue
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Takashi Inoue
IPC分类号： H01L29/778
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/7781
摘要： Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103) of a first III-nitride semiconductor; and a carrier travel layer (104) of a second III-nitride semiconductor. The undercoat layer (103) (101) and the carrier travel layer (104) is formed on the substrate in this order. The field effect transistor includes source/drain electrodes (105, 106) in ohmic contact, and a gate electrode (107) in Schottky contact directly or via another layer on the carrier travel layer (104). The undercoat layer (103) has an average lattice constant greater than that of the carrier travel layer (104) and a band gap greater than that of the carrier travel layer (104).
摘要翻译：提供了能够降低接触电阻，具有小的电流崩溃的半导体器件，并且可以在高频操作时提高夹断特性。使用纤锌矿（具有（0001）作为主面）的III型氮化物半导体的场效应晶体管包括：衬底（101）; 第一III族氮化物半导体的底涂层（103）和第二III族氮化物半导体的载流子行进层（104）。底涂层（103）（101）和载体移动层（104）依次形成在基板上。场效应晶体管包括欧姆接触的源极/漏极（105,106）和直接或通过载流子行进层（104）上的另一层的肖特基接触的栅电极（107）。底涂层（103）的平均晶格常数大于载体移动层（104）的平均晶格常数，并且带隙大于载流子行进层（104）的平均晶格常数。

67. 发明申请

US20090230430A1 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US20090230430A1
公开(公告)日：2009-09-17
申请号：US11921857
申请日：2006-06-12
申请人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
发明人： Hironobu Miyamoto , Yuji Ando , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota , Aklo Wakejima , Kensuke Kasahara , Yasuhiro Murase , Kohji Matsunaga , Katsumi Yamanoguchi , Hidenori Shimawaki
IPC分类号： H01L29/78
CPC分类号： H01L29/404 , H01L29/7783 , H01L29/7787 , H01L29/802 , H01L29/812
摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.
摘要翻译：场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极（118）。第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠（113）表示为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

68. 发明申请

US20090008678A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090008678A1
公开(公告)日：2009-01-08
申请号：US12279010
申请日：2007-01-29
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201
摘要： An electron supply layer (13) is a layer which forms a heterojunction with a channel layer (12) and contains InzAlxGa1-zxN (0≦z
摘要翻译：电子供给层（13）是与沟道层（12）形成异质结并含有In z Al x Ga 1-z x N（0 <= z <1,0 x1 / 2 <= xa <？in-line-formula description =“In-line Formulas”end =“lead”？> x1 <= 0.3。<？in-line-formula description =“In-line Formulas”end = 尾巴“？>

69. 发明申请

US20080179743A1 Electrode, method for producing same and semiconductor device using same 有权
标题翻译：电极及其制造方法以及使用该电极的半导体装置
公开(公告)号：US20080179743A1
公开(公告)日：2008-07-31
申请号：US12007218
申请日：2008-01-08
申请人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Takashi Inoue , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Takashi Inoue , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L29/45 , H01L21/283
CPC分类号： H01L29/452 , H01L21/28 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
摘要翻译：提供了一种获得具有低接触电阻和较小表面粗糙度的电极的技术。提供了一种电极，其包括半导体膜101，以及顺序地依次层叠在半导体膜101上的第一金属层102和第二金属层103，其特征在于，第一金属膜102由Al形成，第二金属层103 金属膜103由选自Nb，W，Fe，Hf，Re，Ta和Zr中的至少一种金属形成。

70. 发明授权

US07071526B2 Semiconductor device having Schottky junction electrode 失效
标题翻译：具有肖特基结电极的半导体器件
公开(公告)号：US07071526B2
公开(公告)日：2006-07-04
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译：提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。

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