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    • 66. 发明授权
    • Multilayer ceramic capacitor
    • 多层陶瓷电容器
    • US06266230B1
    • 2001-07-24
    • US09339521
    • 1999-06-24
    • Junichi KatoTakuya IshiiKoji YoshidaTsutomu NishimuraYoshimasa Yabu
    • Junichi KatoTakuya IshiiKoji YoshidaTsutomu NishimuraYoshimasa Yabu
    • H01G406
    • H01G4/1227
    • The present invention provides a multilayer ceramic capacitor in which electrode metal layers and dielectric ceramic layers are laminated alternately and its dielectric constant peak is present at a temperature below −50° C. The multilayer ceramic capacitor is at least one selected from a multilayer ceramic capacitor to be incorporated into an electric circuit in which an electric field of at least 200 V/mm is applied to dielectric layers as a DC bias electric field and an alternating current at a frequency of at least 20 kHz is superimposed and a multilayer ceramic capacitor to be incorporated into an electric circuit in which an electric field of at least 200 V/mm is applied to dielectric layers as an AC electric field. As the dielectric ceramic, a ceramic containing lead atoms whose amount is indicated by being measured in the form of PbO, which is at least 30 mol %, particularly a compound with a perovskite structure represented by ABO3 is used. Thus, an inexpensive large-capacity multilayer capacitor that has thermal resistance and is stable for a high DC bias voltage and a high frequency voltage, and a low loss switching power supply using this capacitor can be provided.
    • 本发明提供了一种多层陶瓷电容器,其中电极金属层和电介质陶瓷层交替层叠,其介电常数峰值存在于低于-50℃的温度。多层陶瓷电容器是选自多层陶瓷电容器 被掺入电路中,其中将至少200V / mm的电场施加到电介质层作为DC偏置电场,并且以至少20kHz的频率的交流电叠加,并将多层陶瓷电容器叠加到 被并入到电介质层中施加至少200V / mm的电场作为AC电场的电路中。 作为电介质陶瓷,使用含有铅原子的陶瓷,该铅原子的量以PbO的形式测定,其为至少30mol%,特别是由ABO 3表示的具有钙钛矿结构的化合物。 因此,可以提供具有耐热性并且对于高直流偏压和高频电压是稳定的便宜的大容量多层电容器,以及使用该电容器的低损耗开关电源。
    • 68. 发明授权
    • Semiconductor device and method for fabricating the same
    • 半导体装置及其制造方法
    • US6147379A
    • 2000-11-14
    • US58803
    • 1998-04-13
    • Atsushi HoriJunichi KatoShinji OdanakaSeiki OguraKaori Akamatsu
    • Atsushi HoriJunichi KatoShinji OdanakaSeiki OguraKaori Akamatsu
    • H01L21/8247H01L27/115H01L29/788H01L29/792
    • H01L29/7885
    • The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.
    • 本发明的非易失性半导体存储器件包括:半导体衬底,具有包括第一电平的第一表面区域,低于第一电平的第二电平的第二表面区域和连接第一和第二电极的台阶侧区域的表面 表面区域 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域,其形成在半导体衬底的表面中,以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及经由第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一表面区域是形成在第二表面区域上的外延生长层的上表面。 漏极区域包括:形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层; 以及连接到低浓度杂质层并形成在远离沟道区的区域中的高浓度杂质层。 低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。