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61. 发明授权

US07486560B2 Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines 有权
标题翻译：用于制造使用反转位线的虚拟接地阵列结构的装置和相关方法
公开(公告)号：US07486560B2
公开(公告)日：2009-02-03
申请号：US11424748
申请日：2006-06-16
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L29/76
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/12 , H01L27/0207 , H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
摘要翻译：虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

62. 发明授权

US07474562B2 Method of forming and operating an assisted charge memory device 有权
标题翻译：形成和操作辅助电荷存储器件的方法
公开(公告)号：US07474562B2
公开(公告)日：2009-01-06
申请号：US11292024
申请日：2005-12-01
申请人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
发明人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/42332 , H01L29/7887 , H01L29/7923
摘要： A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge trapping layer always has a fixed high threshold voltage (Vt) level which is the assisted charge for the AC-memory cell. The other side (data-side) is used for memory operations.
摘要翻译：提供了形成辅助电荷存储器（AC-存储器）单元的方法。该方法使用包括双面电荷捕获层的双面电荷陷阱存储单元。在双面电荷俘获层的至少一部分中形成电荷。双面电荷捕获层的一侧（AC侧）总是具有固定的高阈值电压（Vt）电平，其为AC存储单元的辅助电荷。另一方（数据端）用于存储器操作。

63. 发明申请

US20080266977A1 METHOD FOR HIGH SPEED PROGRAMMING OF A CHARGE TRAPPING MEMORY WITH AN ENHANCED CHARGE TRAPPING SITE 有权
标题翻译：具有增强电荷捕捉位置的电荷捕捉存储器的高速编程方法
公开(公告)号：US20080266977A1
公开(公告)日：2008-10-30
申请号：US11741917
申请日：2007-04-30
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0466
摘要： A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions.
摘要翻译：使用接通模式辅助充电（TOM-AC）操作来高速编程和擦除电荷俘获存储器的方法。电荷俘获存储器包括覆盖衬底主体的电荷捕获结构，源极和漏极区域。电荷捕获结构包括覆盖介电层的电荷捕获层。电荷捕获层具有辅助电荷位置（也称为AC位点，AC侧或第一电荷捕获位点）和数据位点（也称为数据侧或第二电荷捕获位点）。最初，为了将电荷捕获存储单元置于TOM操作中，通过FN注入将电荷俘获存储单元的AC位置和数据位都擦除到负阈值电压-Vt，从而引起空穴电荷在源极和漏极区之间引起的沟道。

64. 发明申请

US20080258204A1 MEMORY STRUCTURE AND OPERATING METHOD THEREOF 审中-公开
标题翻译：内存结构及其操作方法
公开(公告)号：US20080258204A1
公开(公告)日：2008-10-23
申请号：US11737961
申请日：2007-04-20
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792 , G11C11/34
CPC分类号： H01L29/792 , G11C5/02 , G11C11/404 , G11C11/4076 , G11C2211/4016 , H01L21/8221 , H01L27/0688 , H01L27/10805 , H01L27/10873 , H01L27/11 , H01L27/115 , H01L27/11568 , H01L27/11578
摘要： A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed on the block layer. The doped regions are disposed respectively in the substrate on the two sides of the conducting layer.
摘要翻译：在本发明中提供了包括衬底，电荷俘获层，阻挡层，导电层和两个掺杂区域的存储器结构。电荷捕获层设置在基板上。阻挡层设置在电荷捕获层上。导电层设置在阻挡层上。掺杂区域分别设置在导电层两侧的衬底中。

65. 发明申请

US20080251831A1 Semiconductor structure and process for reducing the second bit effect of a memory device 有权
标题翻译：用于降低存储器件的第二位效应的半导体结构和工艺
公开(公告)号：US20080251831A1
公开(公告)日：2008-10-16
申请号：US11786078
申请日：2007-04-10
申请人： Chao-I Wu , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568
摘要： A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.
摘要翻译：一种非易失性存储单元，其能够存储具有非导电电荷捕获电介质的两比特的信息，例如氮化硅，其与至少一个电介质层（例如氧化物）相关联地与P型衬底相结合，以及公开了在两个源极/漏极区域之间植入衬底的阱区域中的N型沟道。 N型通道实现了反向层，而没有向存储单元的栅极施加偏置电压。一种在单元的P型衬底中嵌入N型沟道的方法，其中N型沟道将存储单元的未编程或编程的电压阈值降低到低于不存在N型沟道的值被披露。 N型通道减小了第二位效应，使得位的编程和非编程电压阈值之间的操作窗口变宽。

66. 发明申请

US20080217679A1 MEMORY UNIT STRUCTURE AND OPERATION METHOD THEREOF 审中-公开
标题翻译：存储单元结构及其操作方法
公开(公告)号：US20080217679A1
公开(公告)日：2008-09-11
申请号：US11683768
申请日：2007-03-08
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/792 , G11C16/0475 , H01L29/513
摘要： A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 1011 cm−2eV−1 to 1013 cm−2eV−1.
摘要翻译：提出了存储单元。存储单元包括Si衬底，形成在Si衬底上的俘获层，形成在捕获层的任一侧上的Si衬底中的第一和第二掺杂区域，形成在俘获层上的栅极，形成的第一氧化物层在栅极和捕获层之间形成在Si衬底和捕获层之间形成的高Dit材料层，以及形成在高Dit材料层和捕获层之间的第二氧化物层，其中界面陷阱密度（Dit）在高Dit材料层和Si衬底之间的距离为10psi -2.2eV至-100nm范围内， 13

67. 发明申请

US20080186779A1 SEMICONDUCTOR DEVICE AND MEMORY AND METHOD OF OPERATING THEREOF 有权
标题翻译：半导体器件和存储器及其操作方法
公开(公告)号：US20080186779A1
公开(公告)日：2008-08-07
申请号：US11670600
申请日：2007-02-02
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34 , H01L27/115
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/105 , H01L27/11568
摘要： A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively.
摘要翻译：提供了适用于嵌入式存储器的存储器。存储器包括衬底，栅极，电荷俘获栅极电介质层，源极和漏极。栅极设置在衬底上方。电荷捕获栅极电介质层设置在栅极和衬底之间。源极和漏极分别设置在栅极旁边的衬底中。

68. 发明申请

US20080121980A1 Bottom Dielectric Structures and High-K Memory Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window 审中-公开
标题翻译：存储器件中的底部介质结构和高K存储器结构以及用于扩展第二位操作窗口的方法
公开(公告)号：US20080121980A1
公开(公告)日：2008-05-29
申请号：US11425553
申请日：2006-06-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/14 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/66833
摘要： Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).
摘要翻译：描述了用于增加具有多个存储器单元的电荷俘获存储器中的存储器操作窗口的方法和结构，其中每个存储器单元能够存储每个存储器单元的多个位。在本发明的第一方面中，通过施加正栅极电压+ Vg来将存储器单元擦除到负电压电平来描述用于增加每位单元2位存储器中的存储器操作窗口的第一种方法。或者，将负栅极电压-Vg施加到每单元存储器2位，以将存储单元擦除为负电压电平。增加存储器操作窗口的第二种方法是将存储器单元擦除到低于初始电压阈值电平的电压电平。这两种擦除方法可以在编程步骤（即，预编程擦除操作）之前或在编程步骤（即，编程后擦除操作）之后实现。

69. 发明申请

US20070297240A1 Methods and Structures for Expanding a Memory Operation Window and Reducing a Second Bit Effect 有权
标题翻译：扩展存储器操作窗口和减少第二位效应的方法和结构
公开(公告)号：US20070297240A1
公开(公告)日：2007-12-27
申请号：US11425482
申请日：2006-06-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0475 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923
摘要： Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).
摘要翻译：描述了用于增加具有多个存储器单元的电荷俘获存储器中的存储器操作窗口的方法和结构，其中每个存储器单元能够存储每个存储器单元的多个位。在本发明的第一方面中，通过施加正栅极电压+ Vg来将存储器单元擦除到负电压电平来描述用于增加每位单元2位存储器中的存储器操作窗口的第一种方法。或者，将负栅极电压-Vg施加到每单元存储器2位，以将存储单元擦除为负电压电平。增加存储器操作窗口的第二种方法是将存储器单元擦除到低于初始电压阈值电平的电压电平。这两种擦除方法可以在编程步骤（即，预编程擦除操作）之前或在编程步骤（即，编程后擦除操作）之后实现。

70. 发明申请

US20070291541A1 An Apparatus and Associated Method for Making a Virtual Ground Array Structure that Uses Inversion Bit Lines 有权
标题翻译：用于制造使用反转位线的虚拟地阵列结构的装置和相关方法
公开(公告)号：US20070291541A1
公开(公告)日：2007-12-20
申请号：US11424748
申请日：2006-06-16
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/12 , H01L27/0207 , H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
摘要翻译：虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

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