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61. 发明申请

US20090198939A1 LAUNCHING MULTIPLE CONCURRENT MEMORY MOVES VIA A FULLY ASYNCHRONOOUS MEMORY MOVER 失效
标题翻译：启动多个同时存储器通过充分的异步存储器移动
公开(公告)号：US20090198939A1
公开(公告)日：2009-08-06
申请号：US12024690
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3851 , G06F12/10
摘要： A data processing system has an asynchronous memory mover, which includes multiple sets of registers for storing addressing and control parameters utilized to generate one or more asynchronous memory move (AMM) operations. The memory mover detects a receipt of a first set of parameters in a first set of registers from the processor. The processor forwards the parameters after the processor initiates a data move in virtual address space, utilizing a source effective address and a destination effective address. The memory mover responds to receiving the first set of parameters by generating and launching a first asynchronous memory move (AMM) operation. When the memory mover receives a second set of parameters in a second set of registers before the first AMM operation completes, the memory mover generates and launches a second AMM operation concurrently with the first AMM operation if no address conflicts exist.
摘要翻译：数据处理系统具有异步存储器移动器，其包括用于存储用于生成一个或多个异步存储器移动（AMM）操作的寻址和控制参数的多组寄存器。存储器移动器检测来自处理器的第一组寄存器中的第一组参数的接收。处理器在虚拟地址空间中启动数据移动后，使用源有效地址和目标有效地址，处理器转发参数。存储器移动器响应于通过生成和启动第一异步存储器移动（AMM）操作来接收第一组参数。当存储器移动器在第一个AMM操作完成之前在第二组寄存器中接收到第二组参数时，如果不存在地址冲突，则存储器移动器生成并与第一个AMM操作同时启动第二个AMM操作。

62. 发明申请

US20090198908A1 METHOD FOR ENABLING DIRECT PREFETCHING OF DATA DURING ASYCHRONOUS MEMORY MOVE OPERATION 失效
标题翻译：用于在异步存储器运行期间实现数据的直接预先提取的方法
公开(公告)号：US20090198908A1
公开(公告)日：2009-08-06
申请号：US12024598
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： RAVI K. ARIMILLI , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30087 , G06F9/3017 , G06F9/30185 , G06F9/3834 , G06F9/3877
摘要： While an AMM operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers a cache injection by the AMM mover (or memory controller) of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache. The memory controller also forwards the next cache lines in the sequence of data to the L2 cache and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller does not overrun the upper caches, by placing moved data into only a subset of the available cache lines of the upper level cache.
摘要翻译：当AMM操作正在进行时，来自源有效地址或目的地有效地址的数据的预取请求触发AMM移动器（或存储器控制器）从在物理存储器中移动的数据流中的相关数据的高速缓存注入。存储器控制器将第一预取行转发到预取引擎和L1缓存。存储器控制器还将数据序列中的下一个高速缓存行转发到L2高速缓存以及随后的一组高速缓存行到L3高速缓存。存储器控制器然后将剩余的数据转发到目的地存储器位置。通过缓存高速缓存中的数据流，而不是将所有移动的数据放在内存中，可以快速访问预取数据。此外，通过将移动的数据仅放置在高级缓存的可用高速缓存行的一部分中，存储器控制器不会超过上部高速缓存。

63. 发明申请

US20060095535A1 System and method for movement of non-aligned data in network buffer model 有权
标题翻译：网络缓冲模型中非对齐数据移动的系统和方法
公开(公告)号：US20060095535A1
公开(公告)日：2006-05-04
申请号：US10959801
申请日：2004-10-06
申请人： Rama Govindaraju , Chulho Kim , Hanhong Xue
发明人： Rama Govindaraju , Chulho Kim , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： H04L47/10
摘要： A method is provided for transferring data between first and second nodes of a network. Such method includes requesting first data to be transferred by a first upper layer protocol (ULP) operating on the first node of the network; and buffering second data for transfer to the second node by a lower protocol layer lower than the first ULP, the second data including an integral number of standard size units of data including the first data. The method further includes posting the second data to the network for delivery to the second node; receiving the second data at the second node; and from the received data, delivering the first data to a second ULP operating on the second node. The method is of particular application when transferring the data in unit size is faster than transferring the data in other than unit size.
摘要翻译：提供了一种用于在网络的第一和第二节点之间传送数据的方法。这种方法包括通过在网络的第一节点上操作的第一上层协议（ULP）请求首先传送的数据; 以及缓冲第二数据以通过低于所述第一ULP的较低协议层传送到所述第二节点，所述第二数据包括包括所述第一数据的标准大小数据单元的整数。该方法还包括将第二数据发布到网络以传送到第二节点; 在第二节点处接收第二数据; 并且从所接收的数据中，将第一数据传送到在第二节点上操作的第二ULP。当传输单位大小的数据比传送除单位大小之外的数据更快时，该方法是特别应用的。

64. 发明申请

US20050283577A1 Facilitating communication within shared memory environments using lock-free queues 有权
标题翻译：促进使用无锁队列的共享内存环境中的通信
公开(公告)号：US20050283577A1
公开(公告)日：2005-12-22
申请号：US10874024
申请日：2004-06-22
申请人： Rajeev Sivaram , Hanhong Xue
发明人： Rajeev Sivaram , Hanhong Xue
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/526 , G06F9/546
摘要： Lock-free queues of a shared memory environment are used to facilitate communication within that environment. The lock-free queues can be used for interprocess communication, as well as intraprocess communication. The lock-free queues are structured to minimize the use of atomic operations when performing operations on the queues, and to minimize the number of enqueue/dequeue operations to be performed on the queues.
摘要翻译：使用共享内存环境的无锁队列来促进该环境中的通信。无锁队列可用于进程间通信以及进程间通信。无锁队列的结构是在对队列执行操作时最小化原子操作的使用，并最大限度地减少队列上要执行的入队/出队操作数。

65. 发明授权

US08417778B2 Collective acceleration unit tree flow control and retransmit 失效
标题翻译：集体加速单位树流控制和重传
公开(公告)号：US08417778B2
公开(公告)日：2013-04-09
申请号：US12640208
申请日：2009-12-17
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.
摘要翻译：提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传送集合分组。系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失数据包

66. 发明授权

US08356151B2 Reporting of partially performed memory move 有权
标题翻译：报告部分执行内存移动
公开(公告)号：US08356151B2
公开(公告)日：2013-01-15
申请号：US12024504
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Ronald N. Kalla , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F9/30043 , G06F12/0831 , G06F12/0862 , G06F12/1027
摘要： A method performed in a data processing system initiates an asynchronous memory move (AMM) operation, whereby a processor performs a move of data in virtual address space from a first effective address to a second effective address and forwards parameters of the AMM operation to asynchronous memory mover logic for completion of the physical movement of data from a first memory location to a second memory location. The processor executes a second operation, which checks a status of the completion of the data move and returns a notification indicating the status. The notification indicates a status, which includes one of: data move in progress; data move totally done; data move partially done; data move cannot be performed; and occurrence of a translation look-aside buffer invalidate entry (TLBIE) operation. The processor initiates one or more actions in response to the notification received.
摘要翻译：在数据处理系统中执行的方法启动异步存储器移动（AMM）操作，由此处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并将AMM操作的参数转发到异步存储器用于完成数据从第一存储器位置到第二存储器位置的物理移动的移动器逻辑。处理器执行第二操作，其检查数据移动完成的状态，并返回指示状态的通知。该通知表示状态，其中包括：数据移动进行中的一个; 数据移动完成; 数据移动部分完成; 无法执行数据移动; 以及出现翻译后备缓冲区无效条目（TLBIE）操作。处理器响应于收到的通知发起一个或多个动作。

67. 发明授权

US08245004B2 Mechanisms for communicating with an asynchronous memory mover to perform AMM operations 有权
标题翻译：与异步存储器移动器进行通信以执行AMM操作的机制
公开(公告)号：US08245004B2
公开(公告)日：2012-08-14
申请号：US12024560
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system includes a set of architected registers within which the processor places state and other information to communicate with the asynchronous memory mover in order to initiate and control an AMM operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation in response to receiving a set of parameters within the architected registers, which parameters are associated with an AMM store instruction executed by the processor to initiates a move of data in virtual space before placing the information in the architected registers. The architected registers are processor architected registers, defined on a per thread basis by a compiler, or memory mapped architected registers allocated for communicating with the asynchronous memory mover during a bind and subsequent execution of an application. The architected registers are also utilized to store state information to enable a restore to a point before execution of the AMM operation.
摘要翻译：数据处理系统包括一组架构寄存器，处理器将处理器置于与异步存储器移动器通信的状态和其它信息，以启动和控制AMM操作。异步存储器移动器响应于在结构化寄存器内接收到一组参数而执行异步存储器移动（AMM）操作，哪些参数与处理器执行的AMM存储指令相关联，以在放置之前启动虚拟空间中的数据移动建筑登记册中的信息。架构寄存器是由编译器在每个线程基础上定义的处理器架构寄存器，或者在应用程序的绑定和后续执行期间分配用于与异步存储器移动器进行通信的内存映射架构寄存器。架构寄存器还用于存储状态信息，以便在执行AMM操作之前恢复到一个点。

68. 发明授权

US08146094B2 Guaranteeing delivery of multi-packet GSM messages 失效
标题翻译：保证多分组GSM消息的传送
公开(公告)号：US08146094B2
公开(公告)日：2012-03-27
申请号：US12024678
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F13/00 , G06F9/46 , G06F15/16 , H04J1/16 , H04B7/005 , H04B1/44
CPC分类号： H04L1/1642 , G06F9/542
摘要： A target task ensures complete delivery of a global shared memory (GSM) message from an originating task to the target task. The target task's HFI receives a first of multiple GSM packets generated from a single GSM message sent from the originating task. The HFI logic assigns a sequence number and corresponding tuple to track receipt of the complete GSM message. The sequence number is unique relative to other sequence numbers assigned to GSM messages that have not been completely received from the initiating task. The HFI updates a count value within the tuple, which comprises the sequence number and the count value for the first GSM packet and for each subsequent GSM packet received for the GSM message. The HFI determines when receipt of the GSM message is complete by comparing the count value with a count total retrieved from the packet header.
摘要翻译：目标任务确保从始发任务到目标任务的全局共享存储器（GSM）消息的完全传递。目标任务的HFI接收从发起任务发送的单个GSM消息产生的多个GSM分组中的第一个。 HFI逻辑分配序列号和对应的元组来跟踪完整GSM消息的接收。相对于分配给尚未完全从发起任务接收的GSM消息的其他序列号，序列号是唯一的。 HFI更新元组内的计数值，其包括第一GSM分组的序列号和计数值以及为GSM消息接收的每个后续GSM分组。通过将计数值与从分组报头检索的计数总数进行比较，HFI确定接收到GSM消息的完成。

69. 发明授权

US07991981B2 Completion of asynchronous memory move in the presence of a barrier operation 失效
标题翻译：在存在障碍操作的情况下完成异步存储器移动
公开(公告)号：US07991981B2
公开(公告)日：2011-08-02
申请号：US12024513
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/30087 , G06F9/30032 , G06F9/3004 , G06F9/3834 , G06F9/3885 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The processor receives the AMM ST instruction after executing the barrier operation (or SYNC instruction) and before the completion of the barrier operation or SYNC on the system fabric. The processor continues executing the AMM ST instruction, which performs a move in virtual address space and then triggers the generation of the AMM operation. The AMM operation proceeds while the barrier operation continues, independent of the processor. The processor stops further execution of all other memory access requests, excluding AMM ST instructions that are received after the barrier operation, but before completion of the barrier operation.
摘要翻译：数据处理系统中的方法，通过该方法，处理器执行异步存储器移动（AMM）存储（ST）指令以与正在进行的（未完成）先前发布的屏障操作并行地完成对应的AMM操作。执行屏障操作（或SYNC指令）后，在系统结构上完成屏障操作或SYNC之前，处理器接收AMM ST指令。处理器继续执行AMM ST指令，其在虚拟地址空间中执行移动，然后触发AMM操作的生成。无障碍操作继续进行，与处理器无关，AMM操作继续进行。处理器停止所有其他存储器访问请求的进一步执行，排除在屏障操作之后但在屏障操作完成之前接收的AMM ST指令。

70. 发明授权

US07930504B2 Handling of address conflicts during asynchronous memory move operations 失效
标题翻译：在异步存储器移动操作期间处理地址冲突
公开(公告)号：US07930504B2
公开(公告)日：2011-04-19
申请号：US12024575
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/10 , G06F9/30032 , G06F9/3834 , G06F9/3861 , G06F12/0815 , G06F12/1027 , G06F13/28
摘要： A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation.
摘要翻译：数据处理系统中的方法，其中处理器处理由异步存储器移动（AMM）操作的异步存储器移动器执行期间发生的冲突。异步存储器移动器执行异步存储器移动（AMM）操作，通过该操作将实际数据从源移动到目的地存储器位置，与处理器无关。存储器移动器设置一个标志位，以指示异步存储器移动器当前在存储器上执行AMM操作。当处理器接收到存储器访问操作时，处理器在发出新的存储器访问操作之前检查标志位的值，并且检查AMM操作的相关联的地址以确定可能的地址冲突。然后，处理器评估并响应地址冲突，以防止在AMM操作期间数据损坏。

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