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61. 发明申请

US20100301412A1 Power integrated circuit device with incorporated sense FET 有权
标题翻译：功率集成电路器件，内置有感应FET
公开(公告)号：US20100301412A1
公开(公告)日：2010-12-02
申请号：US12455187
申请日：2009-05-29
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L27/088
CPC分类号： H01L29/772 , H01L27/0629 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/7835
摘要： In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.
摘要翻译：在一个实施例中，功率集成电路器件包括形成在高电阻率衬底上的主横向高电压场效应晶体管（HVFET）和相邻定位的横向感测FET。感测电阻器形成在设置在HVFET和感测FET之间的衬底区域中的阱区中。寄生衬底电阻器形成为与HVFET的源极区域和感测FET之间的感测电阻器并联电连接。两个晶体管器件共享共同的漏极和栅电极。当主横向HVFET和感测FET处于导通状态时，在与流过横向HVFET的第一电流成比例的第二源极金属层处产生电压电位。

62. 发明申请

US20090072302A1 Gate metal routing for transistor with checkerboarded layout 有权
标题翻译：晶体管的栅极金属布线，具有棋盘布局
公开(公告)号：US20090072302A1
公开(公告)日：2009-03-19
申请号：US12291569
申请日：2008-11-12
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

63. 发明申请

US20080197396A1 Gate metal routing for transistor with checkerboarded layout 有权
标题翻译：晶体管的栅极金属布线，具有棋盘布局
公开(公告)号：US20080197396A1
公开(公告)日：2008-08-21
申请号：US11707403
申请日：2007-02-16
申请人： Vijay Parthasarathy
发明人： Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42372 , H01L29/4238
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

64. 发明授权

US07368786B2 Process insensitive ESD protection device 有权
标题翻译：过程不敏感的ESD保护装置
公开(公告)号：US07368786B2
公开(公告)日：2008-05-06
申请号：US11078026
申请日：2005-03-11
申请人： Hongzhong Xu , Richard T. Ida , Vijay Parthasarathy
发明人： Hongzhong Xu , Richard T. Ida , Vijay Parthasarathy
IPC分类号： H01L23/58 , H01L29/78
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.
摘要翻译：提供了LDMOS器件的ESD保护方法和设备。该装置包括两个LDMOS器件，源极，漏极和栅极触点并联耦合。一个是受保护的设备，另一个是保护设备。每个具有源极区，漏极区，栅极，包含源极的第一体阱区域，含有漏极的第二体阱区域和通过漂移区域与第一体阱区域分离的隔离区域，与第一和第二体阱区域分离的隔离区域以及与隔离区域接触的掩埋层。保护装置具有与漏极相同类型的另一区域，将漏极耦合到隔离区域。其漏极连接通过与其隔离区而不是漏极区的接触进行。保护装置的漂移区域希望更小，并且隔离体阱分离比对于受保护的装置大。

65. 发明授权

US08866201B2 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US08866201B2
公开(公告)日：2014-10-21
申请号：US13385264
申请日：2012-02-10
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/66 , H01L29/808 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/10
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，JFET端子处的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

66. 发明申请

US20140187919A1 MPR SLICE SELECTION FOR VISUALIZATION OF CATHETER IN THREE-DIMENSIONAL ULTRASOUND 审中-公开
标题翻译：三维超声波导管可视化MPR选择
公开(公告)号：US20140187919A1
公开(公告)日：2014-07-03
申请号：US14113035
申请日：2012-04-19
申请人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
发明人： Vijay Parthasarathy , Ameet Kumar Jain , Charles Ray Hatt, III , Amish N. Raval
IPC分类号： A61B8/08 , A61B6/12 , A61B5/06 , A61M25/01
CPC分类号： A61B5/062 , A61B6/12 , A61B6/503 , A61B6/5247 , A61B8/0841 , A61B8/0883 , A61B8/4254 , A61B8/466 , A61B8/483 , A61B8/523 , A61B8/5261 , A61B34/20 , A61B2017/00243 , A61B2017/00703 , A61B2034/2051 , A61B2034/2061 , A61B2034/2065 , A61B2090/367 , A61B2090/376 , A61B2090/378 , A61M25/0108 , A61M25/0127 , G06T15/08 , G06T2210/41
摘要： A system employs an interventional tool (30), ultrasound imaging system and a multi-planar reformatting module (40). The interventional tool (30) has one or more image tracking points (31). The ultrasound imaging system includes an ultrasound probe (20) operable for generating an ultrasound volume image (22) of a portion or an entirety of the interventional tool (30) within an anatomical region. The multi-planar reformatting imaging module (40) generates two or more multi- planar reformatting images (41) of the interventional tool (30) within the anatomical region. A generation of the two multi-planar reformatting images (41) includes an identification of each image tracking point (31) within the ultrasound volume image (22), and a utilization of each identified image tracking point (31) as an origin of the multi-planar reformatting images (41).
摘要翻译：系统采用介入工具（30），超声成像系统和多平面重新格式化模块（40）。介入工具（30）具有一个或多个图像跟踪点（31）。超声成像系统包括可操作以在解剖区域内产生介入工具（30）的一部分或全部的超声体积图像（22）的超声探头（20）。多平面重新格式化成像模块（40）在解剖区域内生成介入工具（30）的两个或多个多平面重新格式化图像（41）。两个多平面重新格式化图像（41）的生成包括超声波体积图像（22）内的每个图像跟踪点（31）的识别，以及每个识别的图像跟踪点（31）的利用作为多平面重新格式化图像（41）。

67. 发明授权

US08653583B2 Sensing FET integrated with a high-voltage transistor 有权
标题翻译：感应FET与高压晶体管集成
公开(公告)号：US08653583B2
公开(公告)日：2014-02-18
申请号：US11707586
申请日：2007-02-16
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/76
CPC分类号： H01L29/7815 , H01L29/0696 , H01L29/407 , H01L29/7813
摘要： In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，半导体器件包括主垂直场效应晶体管（FET）和感测FET。主垂直FET和感测FET都形成在半导体材料的柱上。两者共同地形成在衬底上方的柱中的延伸漏极区域，以及形成在柱的相对侧上的电介质中的第一和第二栅极构件。主垂直FET和感测FET的源极区域在第一横向方向上分离并电隔离。在操作中，感测FET对在主垂直FET中流动的电流的一小部分进行采样。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

68. 发明申请

US20120280314A1 Gate Pullback at Ends of High-Voltage Vertical Transistor Structure 审中-公开
标题翻译：高压垂直晶体管结构末端的栅极反馈
公开(公告)号：US20120280314A1
公开(公告)日：2012-11-08
申请号：US13541965
申请日：2012-07-05
申请人： Vijay Parthasarathy , Martin H. Manley
发明人： Vijay Parthasarathy , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7811 , H01L2924/13055 , H01L2924/19043
摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。栅极氧化物在圆形部分处基本上更厚。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

69. 发明申请

US20110233657A1 High-voltage vertical transistor with a varied width silicon pillar 有权
公开(公告)号：US20110233657A1
公开(公告)日：2011-09-29
申请号：US13134504
申请日：2011-06-08
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.

70. 发明申请

US20110073942A1 High-voltage transistor structure with reduced gate capacitance 失效
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US20110073942A1
公开(公告)日：2011-03-31
申请号：US12586890
申请日：2009-09-29
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

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