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61. 发明授权

US06265253B1 Aluminum disposable spacer to reduce mask count in CMOS transistor formation 有权
标题翻译：铝一次性间隔物，以减少CMOS晶体管形成中的掩模数量
公开(公告)号：US06265253B1
公开(公告)日：2001-07-24
申请号：US09305098
申请日：1999-05-05
申请人： Todd Lukanc , Matthew S. Buynoski , Zicheng Gary Ling
发明人： Todd Lukanc , Matthew S. Buynoski , Zicheng Gary Ling
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and aluminum disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum disposable spacers removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using aluminum disposable spacers, which can be easily formed and removed without damage to other structures on the substrate, the critical masking steps for source/drain ion implantation are reduced to two, thereby reducing production costs and increasing manufacturing throughput. By employing sidewall spacers, impurities are prevented from being implanted at the edges of the gates. Thus, when source/drain junctions are formed, as by heating and diffusing the implanted impurities, they are advantageously located proximal to the gate edges, and not under the gates, thereby improving device performance.
摘要翻译：具有优化的连接位置的不同导电类型的半导体器件使用最少数量的临界掩模形成在半导体衬底上。实施例包括在半导体衬底的主表面上形成导电栅极，在栅极的侧表面上的侧壁间隔物和侧壁间隔物上的铝一次性间隔物。然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，去除未屏蔽的栅极上的侧壁间隔物上的铝一次性间隔物，并且形成第二杂质类型的轻或中等掺杂的源极/漏极延伸植入物底物。然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，去除剩余的铝一次性间隔物，并形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。通过使用可以容易地形成和去除的铝一次性间隔件，而不损坏衬底上的其它结构，源/漏离子注入的关键掩蔽步骤减少到两个，从而降低生产成本并提高制造生产量。通过使用侧壁间隔物，防止杂质被植入门的边缘。因此，当形成源极/漏极结时，通过加热和扩散植入的杂质，它们有利地位于栅极边缘附近，而不在栅极下方，从而提高器件性能。

62. 发明授权

US06221706B1 Aluminum disposable spacer to reduce mask count in CMOS transistor formation 失效
标题翻译：铝一次性间隔物，以减少CMOS晶体管形成中的掩模数量
公开(公告)号：US06221706B1
公开(公告)日：2001-04-24
申请号：US09268713
申请日：1999-03-17
申请人： Todd Lukanc , Raymond T. Lee , Zicheng Gary Ling , Matthew S. Buynoski
发明人： Todd Lukanc , Raymond T. Lee , Zicheng Gary Ling , Matthew S. Buynoski
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable aluminum sidewall spacers, which can be easily formed and removed without damage to other structures on the substrate or to the substrate silicon, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.
摘要翻译：使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的MOS半导体器件。实施例包括在半导体衬底的主表面上形成导电栅极和在栅极的侧表面上的一次性铝侧壁间隔物。然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的铝侧壁间隔物，并且在第二杂质类型中形成轻度或中度掺杂的第二杂质类型的源极/漏极延伸植入物基质。然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。然后形成具有第一导电类型的杂质的中等或重的源/漏植入物，除去剩余的铝侧壁间隔物，形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。通过使用可以容易地形成和去除而不损坏衬底或衬底硅上的其它结构的一次性铝侧壁间隔物，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并增加制造吞吐量。

63. 发明授权

US06218282B1 Method of forming low dielectric tungsten lined interconnection system 有权
标题翻译：低介电钨丝互连系统的形成方法
公开(公告)号：US06218282B1
公开(公告)日：2001-04-17
申请号：US09252184
申请日：1999-02-18
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L214763
CPC分类号： H01L21/76852 , H01L21/7682 , H01L23/3171 , H01L23/5222 , H01L2924/0002 , Y10T29/49155 , H01L2924/00
摘要： Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and chemical vapor depositing W to line the interconnection system. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, depositing W by CVD to line the interconnection system and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.
摘要翻译：通过去除层间电介质和化学气相沉积W以对互连系统进行排列，多级半导体器件形成具有降低的寄生电容，而不牺牲结构完整性或电迁移性能。实施例包括在形成第一金属化水平之前沉积介电密封层，例如氮化硅，在形成最后的金属化水平之后去除层间电介质，通过CVD沉积W以使互连系统排列并形成介电保护层，例如，硅烷衍生的氧化物最底层的保护层，最上层的金属化层。

64. 发明授权

US06194299B1 Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon 有权
标题翻译：在多晶硅上制造具有厚金属的低电阻率MOSFET栅极的方法
公开(公告)号：US06194299B1
公开(公告)日：2001-02-27
申请号：US09325021
申请日：1999-06-03
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/31053 , H01L21/3212 , H01L29/4941 , H01L29/6659
摘要： The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the silicide over the polysilicon or the polysilicon of the gate is exposed. The present invention further includes the step of etching away the silicide and a predetermined thickness of the polysilicon if the silicide is exposed and of etching away a predetermined thickness of the polysilicon if the polysilicon is exposed, such that an opening is formed on top of a remaining portion of the polysilicon. In addition, the present invention includes the step of depositing a metal within the opening. In this manner, the gate of the present invention has low resistivity since a relatively thick layer of metal is deposited on the remaining portion of the polysilicon. However, with the present invention, the remaining portion of the polysilicon has a sufficient thickness such that a threshold voltage of the MOSFET is not substantially affected by the metal disposed on top of the remaining portion of the polysilicon.
摘要翻译：本发明是一种用于制造具有低电阻率的栅极的MOSFET（金属氧化物半导体场效应晶体管）的栅极的方法。 MOSFET具有在半导体衬底内制造的漏极区域，源极区域和沟道区域，并且MOSFET最初在沟道区域上具有由设置在栅极电介质上的多晶硅上的硅化物构成的栅极。通常，本发明的方法包括在MOSFET的漏极区域，源极区域和栅极之上沉积第一介电层的步骤。本发明还包括在漏极区域和源极区域上抛光第一电介质层并且在栅极上抛光第一电介质层直至硅化物超过多晶硅或栅极的多晶硅的步骤。本发明还包括如果硅化物被暴露则蚀刻掉硅化物和预定厚度的多晶硅的步骤，并且如果多晶硅被暴露则蚀刻掉预定厚度的多晶硅，使得开口形成在剩余部分的多晶硅。此外，本发明包括在开口内沉积金属的步骤。以这种方式，本发明的栅极具有低电阻率，因为相对较厚的金属层沉积在多晶硅的剩余部分上。然而，利用本发明，多晶硅的剩余部分具有足够的厚度，使得MOSFET的阈值电压基本上不受设置在多晶硅的剩余部分顶部的金属的影响。

65. 发明授权

US5729045A Field effect transistor with higher mobility 失效
标题翻译：场效应晶体管具有较高的迁移率
公开(公告)号：US5729045A
公开(公告)日：1998-03-17
申请号：US626340
申请日：1996-04-02
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L21/265 , H01L21/336 , H01L29/04 , H01L29/10 , H01L31/036
CPC分类号： H01L29/66575 , H01L29/045 , H01L29/1033 , H01L21/26586 , Y10S438/973
摘要： A method of increasing the performance of an FET device by aligning the channel of the FET with the �110! crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45 cc.degree. relative to each other so that, instead of the channel being aligned parallel with the �100! crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the �110! crystal direction. The mobility of the carriers is higher in the �110! crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the �110! crystal direction.
摘要翻译：通过将FET的沟道与{100}硅晶片的[110]晶体方向对准来提高FET器件的性能的方法。 {100}硅晶片和光刻掩模的图像相对于彼此旋转45cc，使得在常规制造中，代替通道对准平行于[100]晶体方向，通道对准大致平行与[110]晶体方向。载流子的迁移率在[110]晶体方向上较高，从而在光刻工艺中仅仅进行微小修改来提高FET的性能。新型FET的结果是其通道与[110]晶体方向大致平行。

66. 发明授权

US4940671A High voltage complementary NPN/PNP process 失效
标题翻译：高压互补NPN / PNP工艺
公开(公告)号：US4940671A
公开(公告)日：1990-07-10
申请号：US853530
申请日：1986-04-18
申请人： J. Barry Small , Matthew S. Buynoski
发明人： J. Barry Small , Matthew S. Buynoski
IPC分类号： H01L21/761 , H01L21/8228
CPC分类号： H01L21/82285 , H01L21/761
摘要： A process is disclosed for forming high-performance high-voltage PNP transistors in a conventional monolithic, planar, PN junction isolated integrated circuit that contains high-performance NPN transistors. The process permits independently optimizing the NPN and PNP transistors.
摘要翻译：公开了用于在包含高性能NPN晶体管的常规单片，平面，PN结隔离集成电路中形成高性能高压PNP晶体管的工艺。该过程允许独立地优化NPN和PNP晶体管。

67. 发明授权

US07679134B1 FinFET device with multiple fin structures 有权
标题翻译： FinFET器件具有多个鳍结构
公开(公告)号：US07679134B1
公开(公告)日：2010-03-16
申请号：US10754515
申请日：2004-01-12
申请人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
发明人： Matthew S. Buynoski , Judy Xilin An , Haihong Wang , Bin Yu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L29/66795
摘要： A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.
摘要翻译：半导体器件包括一组翅片结构。翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

68. 发明授权

US07067349B1 Ion path polymers for ion-motion memory 有权
标题翻译：用于离子运动记忆的离子通道聚合物
公开(公告)号：US07067349B1
公开(公告)日：2006-06-27
申请号：US10968705
申请日：2004-10-19
申请人： Matthew S. Buynoski , Richard P. Kingsborough
发明人： Matthew S. Buynoski , Richard P. Kingsborough
IPC分类号： H01L51/40
CPC分类号： G11C13/0016 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C2213/56 , H01L27/285
摘要： Methods and systems for improving at least one of carrier ion/charge mobility, distribution and permeability in a semiconducting polymer layer of a microelectronic device are disclosed. The methods include forming a semiconducting polymer layer containing at least one semiconducting polymer with one or more ion-complexing side-chain groups. The methods provide for the manufacture of microelectronic devices with one or more of improved carrier ion/charge mobility, distribution and permeability.
摘要翻译：公开了用于改善微电子器件的半导体聚合物层中的载流子离子/电荷迁移率，分布和磁导率中的至少一种的方法和系统。所述方法包括形成含有至少一个具有一个或多个离子络合侧链基团的半导体聚合物的半导体聚合物层。这些方法提供了具有改进的载体离子/电荷迁移率，分布和渗透性中的一种或多种的微电子器件的制造。

69. 发明授权

US06916696B1 Method for manufacturing a memory element 失效
标题翻译：存储元件的制造方法
公开(公告)号：US06916696B1
公开(公告)日：2005-07-12
申请号：US10718459
申请日：2003-11-20
申请人： Matthew S. Buynoski
发明人： Matthew S. Buynoski
IPC分类号： H01L21/8238 , H01L45/00
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/142 , H01L45/1633
摘要： A method for manufacturing the memory device by plasma decomposition of sulfur dioxide. A first copper electrode having a surface is provided. The surface of the first copper electrode may be made amorphous. A copper sulfide layer, CuxS, where 1≦x≦2, is disposed on the copper surface by decomposing sulfur dioxide in an ambient containing excess hydrogen. The copper sulfide layer may be is cuprous sulfide or cupric sulfide. A second copper electrode is coupled to the copper sulfide layer.
摘要翻译：一种通过二氧化硫的等离子体分解来制造记忆装置的方法。提供具有表面的第一铜电极。第一铜电极的表面可以是无定形的。通过在含有过量氢气的环境中分解二氧化硫，铜表面上的铜硫化物层，其中1 <= x <= 2。硫化铜层可以是硫化亚铜或硫化铜。第二铜电极耦合到硫化铜层。

70. 发明授权

US06872644B1 Semiconductor device with non-compounded contacts, and method of making 失效
标题翻译：具有非复合触点的半导体器件及其制造方法
公开(公告)号：US06872644B1
公开(公告)日：2005-03-29
申请号：US10126211
申请日：2002-04-19
申请人： Matthew S. Buynoski , Witold P. Maszara
发明人： Matthew S. Buynoski , Witold P. Maszara
IPC分类号： H01L21/22 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/38
CPC分类号： H01L29/66477 , H01L21/28044
摘要： A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.
摘要翻译：半导体器件包括源极和漏极接触区域，其包括半导体材料和至少一种金属的非复合组合。金属可以包括元素金属，例如金或铝，或者可以包括金属间化合物。接触区域可以通过在器件的源极和漏极上沉积有限量的至少一种金属而形成，并且退火该器件以诱导至少一种金属扩散到源极和漏极中。可以选择退火时间和温度来限制至少一种金属的扩散。

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