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61. 发明申请

US20080237678A1 On-chip memory cell and method of manufacturing same 审中-公开
标题翻译：片上存储单元及其制造方法
公开(公告)号：US20080237678A1
公开(公告)日：2008-10-02
申请号：US11729192
申请日：2007-03-27
申请人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
发明人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L27/10873 , H01L27/10826 , H01L29/785
摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.
摘要翻译：片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

62. 发明授权

US07316949B2 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US07316949B2
公开(公告)日：2008-01-08
申请号：US11248737
申请日：2005-10-11
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

63. 发明申请

US20160308014A1 FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：用于场效应晶体管的通道封口结构的制造
公开(公告)号：US20160308014A1
公开(公告)日：2016-10-20
申请号：US15197563
申请日：2016-06-29
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/423 , H01L29/66 , H01L29/06 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/28079 , H01L21/28194 , H01L29/0673 , H01L29/41775 , H01L29/495 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66606 , H01L29/66636 , H01L29/66742 , H01L29/7834 , H01L29/78618 , H01L29/78696 , Y10S438/926 , Y10S438/957
摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
摘要翻译：描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

64. 发明授权

US09337307B2 Method for fabricating transistor with thinned channel 有权
公开(公告)号：US09337307B2
公开(公告)日：2016-05-10
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

65. 发明授权

US07999298B2 Embedded memory cell and method of manufacturing same 有权
标题翻译：嵌入式存储单元及其制造方法
公开(公告)号：US07999298B2
公开(公告)日：2011-08-16
申请号：US12319101
申请日：2008-12-30
申请人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
发明人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
IPC分类号： H01L27/108
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

66. 发明申请

US20110062520A1 METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL 审中-公开
标题翻译：用于制造具有薄型通道的晶体管的方法
公开(公告)号：US20110062520A1
公开(公告)日：2011-03-17
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/786
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译：描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

67. 发明授权

US07525160B2 Multigate device with recessed strain regions 有权
标题翻译：具有凹陷应变区的多组装置
公开(公告)号：US07525160B2
公开(公告)日：2009-04-28
申请号：US11320309
申请日：2005-12-27
申请人： Jack T. Kavalieros , Justin K. Brask , Suman Datta , Brian S. Doyle , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Suman Datta , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7848
摘要： Embodiments of the invention provide a device with a multiple gates. Stress material within recesses of a device body metal gate may cause a stress in channel regions of the device, thereby improving performance of the device.
摘要翻译：本发明的实施例提供具有多个门的装置。器件金属门的凹槽内的应力材料可能在器件的沟道区域中引起应力，从而提高器件的性能。

68. 发明申请

US20080237719A1 Multi-gate structure and method of doping same 审中-公开
标题翻译：多栅极结构及掺杂方法
公开(公告)号：US20080237719A1
公开(公告)日：2008-10-02
申请号：US11729198
申请日：2007-03-28
申请人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
发明人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803
摘要： A multi-gate structure includes a substrate (110, 210, 410), an electrically insulating layer (120, 220, 420) over the substrate, and a first semiconducting fin (130, 230, 430) above the electrically insulating layer. The first semiconducting fin includes a top region (131, 231, 431), a first side region (132, 232, 432), and a second side region (133, 233, 433). The top region, the first side region, and the second side region have doping concentrations that are substantially equal to each other. The multi-gate structure may be made by depositing a solid source material (510) over the semiconducting fin, and by annealing the multi-gate structure such that dopants from the solid source material diffuse into the semiconducting fin and uniformly dope the top region and the first and second side regions.
摘要翻译：多栅极结构包括衬底（110,210,410），在衬底上方的电绝缘层（120,220,420）以及在电绝缘层上方的第一半导电翅片（130,230,430）。第一半导体鳍片包括顶部区域（131,231,431），第一侧面区域（132,232,432）和第二侧面区域（133,233,433）。顶部区域，第一侧面区域和第二侧面区域具有彼此基本相等的掺杂浓度。多栅极结构可以通过在半导体鳍上沉积固体源材料（510）并且通过退火多栅极结构使得来自固体源材料的掺杂剂扩散到半导体翅片中并且均匀地掺杂顶部区域和第一和第二侧区域。

69. 发明授权

US07858481B2 Method for fabricating transistor with thinned channel 有权
标题翻译：用稀疏通道制造晶体管的方法
公开(公告)号：US07858481B2
公开(公告)日：2010-12-28
申请号：US11154138
申请日：2005-06-15
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译：描述了制造具有减薄沟道区的MOS晶体管的方法。在去除虚拟栅极之后蚀刻沟道区。源极和漏极区域具有相对较低的电阻。

70. 发明申请

US20090140341A1 INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS 有权
标题翻译：独立的N-TIPS多门控晶体管
公开(公告)号：US20090140341A1
公开(公告)日：2009-06-04
申请号：US11948414
申请日：2007-11-30
申请人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L29/785
摘要： Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
摘要翻译：通常描述多栅极晶体管的独立n尖端。在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n端掺杂剂浓度一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

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