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61. 发明授权

US4095234A Recording apparatus for providing lustrous printing 失效
标题翻译：用于提供LUSTROUS打印的记录装置
公开(公告)号：US4095234A
公开(公告)日：1978-06-13
申请号：US813329
申请日：1977-07-05
申请人： Sanai Mito , Shinji Kinpara , Yuji Sumitomo , Toshio Kobayashi
发明人： Sanai Mito , Shinji Kinpara , Yuji Sumitomo , Toshio Kobayashi
IPC分类号： B41J2/01 , B41J11/00 , B41J29/00 , B41M5/00 , G06K15/10 , H04N1/23 , G01D15/18
CPC分类号： B41J11/002
摘要： In a recording apparatus which prints desired symbols on a record receiving member with heat ray absorbing colored material, a heat ray source is provided for heating a printed surface. A roller assembly including a roller impregnated with luster is disposed in such a manner that the printed and heated surface is brought into contact with the impregnated roller. The printed symbols are glossed by the luster since the printed symbols are pre-heated.

62. 发明授权

US09103114B2 Vacuum heat insulation material and manufacturing method therefor 有权
标题翻译：真空隔热材料及其制造方法
公开(公告)号：US09103114B2
公开(公告)日：2015-08-11
申请号：US13063048
申请日：2009-09-09
申请人： Shinya Kojima , Fumie Horibata , Tomohisa Tenra , Toshio Kobayashi
发明人： Shinya Kojima , Fumie Horibata , Tomohisa Tenra , Toshio Kobayashi
IPC分类号： B32B1/06 , B32B3/02 , B32B37/12 , E04B1/80 , F16L59/065
CPC分类号： E04B1/803 , F16L59/065 , Y02A30/242 , Y02B80/12 , Y10T428/231
摘要： A plurality of thin-wall parts (9a) of a sealant layer (7) are formed in a portion continuously changed in the interval of one sealing part (8) and a gas barrier layer (6) of other laminate film (4). At the inner circumferential side between the adjacent thin-wall parts (9a) and the thin-wall part (9a) at the innermost circumferential side and at the outer circumferential side of the thin-wall part (9a) of the outermost circumferential side, a thick-wall part (9b) of the sealant layer (7) is formed. All of the opposing sealant layers (7) between the two adjacent thin-wall parts (9a) are mutually heated and fused, so that an excellent adiabatic performance is maintained for a long period.
摘要翻译：密封剂层（7）的多个薄壁部分（9a）形成在一个密封部分（8）和另一层压薄膜（4）的阻气层（6）的间隔中连续变化的部分。在相邻的薄壁部（9a）与最外周侧的薄壁部（9a）的最内周侧和外周侧的薄壁部（9a）之间的内周侧，形成密封剂层（7）的厚壁部（9b）。两个相邻薄壁部分（9a）之间的所有相对的密封剂层（7）相互加热和熔合，从而长期保持优异的绝热性能。

63. 发明授权

US08823097B2 Protection device with a thin-film resistance connected to plural drain regions 有权
标题翻译：具有连接到多个漏极区域的薄膜电阻的保护装置
公开(公告)号：US08823097B2
公开(公告)日：2014-09-02
申请号：US12621164
申请日：2009-11-18
申请人： Tsutomu Imoto , Toshio Kobayashi
发明人： Tsutomu Imoto , Toshio Kobayashi
IPC分类号： H01L27/06 , H01L29/8605 , H01L29/78 , H01L29/735 , H01L27/02 , H01L29/66 , H01L29/73 , H01L29/08
CPC分类号： H01L29/8605 , H01L27/0277 , H01L29/0821 , H01L29/0847 , H01L29/66659 , H01L29/7304 , H01L29/735 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.
摘要翻译：晶体管型保护器件包括：半导体衬底; 在半导体衬底中形成的第一导电型阱的阱; 在井中形成的第二导电型源极区; 在源极区域的一侧经由栅极绝缘膜在阱上形成的栅电极; 第二导电类型的多个漏极区彼此分开形成，并且分别与栅电极膜正下方的阱部分预定距离分离; 以及电阻连接部，其以预定的电阻连接在所述多个漏极区之间。

64. 发明授权

US08164131B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08164131B2
公开(公告)日：2012-04-24
申请号：US11633292
申请日：2006-12-04
申请人： Toshio Kobayashi , Saori Hara
发明人： Toshio Kobayashi , Saori Hara
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/792 , H01L29/66833 , H01L29/7923
摘要： A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.
摘要翻译：非易失性半导体存储器件包括：具有第一导电性的第一半导体区域; 形成具有第二导电性的沟道反转层的沟道形成区域; 具有第二导电性的第二半导体区域; 具有第二导电性的第三半导体区域; 形成在沟道形成区上的叠层绝缘膜; 以及形成在层叠绝缘膜上的控制电极。叠层绝缘膜从沟道形成区域侧开始依次包括第一绝缘膜，电荷存储膜和第二绝缘膜。控制电极延伸到第二半导体区域和第三半导体区域中的一个之上。除去存在于控制电极的延伸部分与第二半导体区域或第三半导体区域之间的电荷存储膜，并且用第三绝缘膜填充电荷存储膜被除去的部分。

65. 发明授权

US07985619B2 Manufacturing method for semiconductor device embedded substrate 有权
标题翻译：半导体器件嵌入式衬底的制造方法
公开(公告)号：US07985619B2
公开(公告)日：2011-07-26
申请号：US12608383
申请日：2009-10-29
申请人： Toshio Kobayashi , Tadashi Arai , Takaharu Yamano
发明人： Toshio Kobayashi , Tadashi Arai , Takaharu Yamano
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/02333 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/18162 , H01L2224/82
摘要： A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a first wiring pattern on a surface of each of the first insulating layer and the second insulating layer; a sixth step of forming a via-hole from which the first wiring pattern is exposed on the second insulating layer; and a seventh step of forming a second wiring pattern electrically connected on a surface of the second insulating layer.
摘要翻译：一种半导体器件嵌入式衬底的制造方法，包括：准备具有第一绝缘层的半导体器件的第一工序; 制备支撑体的第二步骤，以及将半导体器件布置在支撑体的一个表面上; 在所述支撑体的一个表面上形成第二绝缘层的第三步骤; 去除支撑体的第四步骤; 在第一绝缘层和第二绝缘层的表面上形成第一布线图案的第五步骤; 在所述第二绝缘层上形成从所述第一布线图案露出的通孔的第六步骤; 以及形成电连接在第二绝缘层的表面上的第二布线图案的第七步骤。

66. 发明授权

US07754535B2 Method of manufacturing chip integrated substrate 有权
标题翻译：芯片集成基板的制造方法
公开(公告)号：US07754535B2
公开(公告)日：2010-07-13
申请号：US12123673
申请日：2008-05-20
申请人： Toshio Kobayashi
发明人： Toshio Kobayashi
IPC分类号： H01L23/488
CPC分类号： H05K1/144 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/01047 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K3/284 , H05K3/3436 , H05K2201/10234 , H05K2201/10977 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01005 , H01L2924/01033
摘要： There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 with a copper core 22, polishing a portion of the electrode 21 which is to be bonded to the connecting pad 12, thereby exposing the copper core 22 from the solder coat 23, bonding the exposed portion of the copper core 22 to the bump connecting pad 12 by using a flux non-containing conductive paste 30, thereby bonding the substrates 10 and 20 to each other, and filling a sealing resin 40 in a clearance portion between the substrates 10 and 20.
摘要翻译：提供了通过引线接合将芯片部件13连接到第一基板10的步骤，在第二基板20上提供具有铜芯22的具有焊料涂层23的电极21，抛光电极21的一部分要连接到连接焊盘12，从而将铜芯22从焊料涂层23暴露出来，通过使用焊剂不含导电浆料30将铜芯22的露出部分接合到焊盘连接焊盘12上，从而结合基板10和20彼此之间，并且将密封树脂40填充在基板10和20之间的间隙部分中。

67. 发明申请

US20100155992A1 MOLD RESIN MOLDING METHOD AND MOLD RESIN MOLDING APPARATUS 审中-公开
标题翻译：模具树脂模具和模具树脂成型设备
公开(公告)号：US20100155992A1
公开(公告)日：2010-06-24
申请号：US12644399
申请日：2009-12-22
申请人： Nobuyuki Kurashima , Toshio Kobayashi
发明人： Nobuyuki Kurashima , Toshio Kobayashi
IPC分类号： B29C45/14
CPC分类号： B29C45/14655 , B29C45/0025 , B29C45/02 , B29C45/56 , B29C45/77 , B29C2945/76498 , B29C2945/76735 , B29C2945/76765 , B29C2945/76859 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014
摘要： A mold resin molding method is provided with: providing a semiconductor device including a first wiring board and a second wiring board electrically connected to the first wiring board through a solder ball; providing a metal mold including a die plate which is independently provided to enable an approach/separation to/from the second wiring board; inserting the semiconductor device into a cavity of the metal mold; abutting the die plate on a surface side of the second wiring board through a release film; injecting a mold resin in a void between the first wiring board and the second wiring board while applying a first pressure from the die plate to the second wiring board; and further injecting the mold resin in the void while applying a second pressure which is higher than the first pressure from the die plate to the second wiring board.
摘要翻译：模具树脂成型方法具有：提供包括第一布线板和第二布线板的半导体器件，所述第一布线板和第二布线板通过焊球与第一布线板电连接; 提供包括模板的金属模具，所述模具板独立地设置成能够进入/离开所述第二布线板; 将半导体器件插入到金属模具的空腔中; 通过脱模膜将模板抵靠在第二配线基板的表面侧; 在第一配线板和第二配线板之间的空隙中注入模塑树脂，同时从模板施加第一压力到第二配线板; 并且在将来自模板的第一压力高于第二压接力的第二压力施加到第二配线基板的同时，将模具树脂进一步注入到空隙中。

68. 发明申请

US20100025081A1 WIRING SUBSTRATE AND ELECTRONIC COMPONENT DEVICE 审中-公开
标题翻译：接线基板和电子部件装置
公开(公告)号：US20100025081A1
公开(公告)日：2010-02-04
申请号：US12492560
申请日：2009-06-26
申请人： Tadashi Arai , Toshio Kobayashi
发明人： Tadashi Arai , Toshio Kobayashi
IPC分类号： H05K1/16 , H05K1/11 , H05K1/09
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49816 , H01L23/49833 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2224/0401
摘要： A wiring substrate includes a frame-shaped reinforcing plate in which an opening portion is provided in a center portion, an interposer arranged in the opening portion of the reinforcing plate and having such a structure that a wiring layer connected mutually via a through electrode is formed on both surface sides of a substrate respectively, a resin portion filled between a side surface of the interposer and a side surface of the opening portion of the reinforcing plate, and coupling the interposer and the reinforcing plate, and an n-layered (n is an integer of 1 or more) lower wiring layer connected the wiring layer on the lower surface side of the interposer to extend from the interposer to an outer area.
摘要翻译：布线基板包括在中心部分设置有开口部的框状加强板，布置在加强板的开口部中的内插件，并且具有通过贯通电极相互连接的布线层的结构在衬底的两个表面侧分别填充有插入件的侧表面和加强板的开口部分的侧表面之间的树脂部分，并且连接插入件和加强板，并且n层（n是 1个以上的整数）下布线层，其连接在插入件的下表面侧上的布线层，以从插入件延伸到外部区域。

69. 发明授权

US07605424B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07605424B2
公开(公告)日：2009-10-20
申请号：US11846802
申请日：2007-08-29
申请人： Tsutomu Imoto , Toshio Kobayashi , Takayoshi Kato
发明人： Tsutomu Imoto , Toshio Kobayashi , Takayoshi Kato
IPC分类号： H01L29/94
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1037 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.
摘要翻译：一种半导体器件，包括：半导体区域，具有连接到第一半导体表面并且具有相对于第一半导体表面的倾斜的第一半导体面和第二半导体面; 形成在所述第一和第二半导体面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅极，所述栅极绝缘膜包括在所述第一半导体面和所述第二半导体面之间的边界上的一部分; 源极杂质区，形成在所述半导体区域中，以与所述栅极绝缘膜插入在所述源极杂质区域和所述栅极电极之间，与所述第一半导体面内的所述栅电极重叠; 以及至少在第二半导体面的正下方的半导体区域中形成的漏极杂质区域。

70. 发明申请

US20080155820A1 Wiring substrate, manufacturing method thereof, and semiconductor device 有权
标题翻译：配线基板及其制造方法以及半导体装置
公开(公告)号：US20080155820A1
公开(公告)日：2008-07-03
申请号：US11984004
申请日：2007-11-13
申请人： Tadashi Arai , Toshio Kobayashi
发明人： Tadashi Arai , Toshio Kobayashi
IPC分类号： H01L23/48 , H05K3/36
CPC分类号： H01L23/3128 , H01L21/565 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/157 , H01L2924/19041 , Y10T29/49126 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a wiring substrate according to the present invention, a base wiring board is constructed by stacking a plurality of unit wiring boards each having wiring patterns which enable an electrical connection between upper and lower sides, in a state that the plurality of unit wiring boards are connected to each other via a connection terminal, and a silicon interposer is stacked on the base wiring board via a connection terminal, and a resin portion is filled in a gap between the plurality of unit wiring boards as well as a gap between the base wiring board and the silicon interposer, and a resin portion serves as a substrate which integrates the base wiring board and the silicon interposer.
摘要翻译：在本发明的布线基板中，通过在多个单元配线基板为多个单元配线基板的状态下，堆叠多个单元配线基板，该多个单元配线基板具有能够在上下侧之间进行电连接的布线图案通过连接端子彼此连接，并且硅插入件经由连接端子堆叠在基底布线板上，树脂部分填充在多个单元布线板之间的间隙以及基布线板和硅插入件，树脂部分用作将基布线板和硅插入件集成的基板。

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