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61. 发明申请

US20090068804A1 DRAIN EXTENDED PMOS TRANSISTORS AND METHODS FOR MAKING THE SAME 有权
标题翻译：漏极扩展PMOS晶体管及其制造方法
公开(公告)号：US20090068804A1
公开(公告)日：2009-03-12
申请号：US12273850
申请日：2008-11-19
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/0882 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.
摘要翻译：提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

62. 发明授权

US07498652B2 Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof 有权
公开(公告)号：US07498652B2
公开(公告)日：2009-03-03
申请号：US10832009
申请日：2004-04-26
申请人： Shanjen Pan , Sameer Pendharkar , James R. Todd
发明人： Shanjen Pan , Sameer Pendharkar , James R. Todd
IPC分类号： H01L29/93
CPC分类号： H01L29/0847 , H01L21/266 , H01L27/0623 , H01L29/0619 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835 , H01L2029/42388
摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

63. 发明授权

US07468537B2 Drain extended PMOS transistors and methods for making the same 有权
标题翻译：漏极扩展PMOS晶体管及其制造方法
公开(公告)号：US07468537B2
公开(公告)日：2008-12-23
申请号：US11012469
申请日：2004-12-15
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/0882 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.
摘要翻译：提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

64. 发明授权

US07427795B2 Drain-extended MOS transistors and methods for making the same 有权
标题翻译：漏极扩散MOS晶体管及其制造方法
公开(公告)号：US07427795B2
公开(公告)日：2008-09-23
申请号：US10880907
申请日：2004-06-30
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L31/119
CPC分类号： H01L29/7816 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).
摘要翻译：描述了漏极扩散MOS晶体管（T 1，T 2）和半导体器件（102）及其制造方法（202），其中在形成外延硅之前形成p埋层（130） 106），并且在外延硅层（106）中形成漏极扩展MOS晶体管（T 1，T 2）。 p埋层（130）可以形成在用于高侧驱动晶体管（T 2）应用的衬底（104）中的n掩埋层（120）上方，其中p埋层（130）在漏极扩展MOS晶体管（T 2）和n掩埋层（120），以抑制源极（154）和漏极（156）之间的截止状态击穿。

65. 发明申请

US20070246773A1 Drive circuit and drain extended transistor for use therein 有权
标题翻译：用于其中的驱动电路和漏极延伸晶体管
公开(公告)号：US20070246773A1
公开(公告)日：2007-10-25
申请号：US11408692
申请日：2006-04-20
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1087 , H01L29/41 , H01L29/41725 , H01L29/42368 , H01L29/66659 , H03K19/00384
摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
摘要翻译：晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。在第一半导体区域和第二半导体区域之间存在界面。晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。还描述了一种混合技术电路。

66. 发明授权

US07235451B2 Drain extended MOS devices with self-aligned floating region and fabrication methods therefor 有权
标题翻译：排水扩展MOS器件具有自对准浮动区域及其制造方法
公开(公告)号：US07235451B2
公开(公告)日：2007-06-26
申请号：US10378402
申请日：2003-03-03
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L29/0615 , H01L29/0619 , H01L29/0847 , H01L29/7835
摘要： Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.
摘要翻译：公开了半导体器件及其制造方法，其中漏极扩展MOS晶体管包括靠近晶体管栅极的一端的自对准浮置区，并掺杂有第一类型掺杂剂以减少通道热载流子劣化，以及相反地掺杂的第一源极/漏极在半导体本体中与栅极结构的第一端横向间隔开。该器件还可以包括掺杂到比浮置区域更低的浓度的复现区域，以便于改进的击穿电压性能。公开了一种在半导体器件中制造漏极扩展MOS晶体管的方法，包括：向半导体本体中的浮置区域提供第一掺杂物，所述浮置区域与栅极结构的第一端自对准，并提供第二掺杂剂到源极 /半导体主体的漏极，其中第一和第二掺杂剂是不同的。

67. 发明授权

US07135373B2 Reduction of channel hot carrier effects in transistor devices 有权
公开(公告)号：US07135373B2
公开(公告)日：2006-11-14
申请号：US10670434
申请日：2003-09-23
申请人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
发明人： Pinghai Hao , Shanjen Pan , Sameer Pendharkar
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

68. 发明申请

US20060124999A1 Drain extended PMOS transistors and methods for making the same 有权
标题翻译：漏极扩展PMOS晶体管及其制造方法
公开(公告)号：US20060124999A1
公开(公告)日：2006-06-15
申请号：US11012469
申请日：2004-12-15
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/0882 , H01L29/1083 , H01L29/42368 , H01L29/66689
摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.
摘要翻译：提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a）及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和晶体管背栅（126），以增加击穿电压性能而不增加外延厚度。

69. 发明申请

US20060011974A1 Drain-extended MOS transistors with diode clamp and methods for making the same 有权
标题翻译：具有二极管钳位的漏极扩散型MOS晶体管及其制造方法
公开(公告)号：US20060011974A1
公开(公告)日：2006-01-19
申请号：US10890648
申请日：2004-07-14
申请人： Sameer Pendharkar
发明人： Sameer Pendharkar
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/1083 , H01L27/0629 , H01L29/66689 , H01L29/7816 , H01L29/7818
摘要： High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108, 156) to increase the breakdown voltage.
摘要翻译：提出了高侧扩展漏极MOS驱动晶体管（T 2），其中扩展漏极（108,156）通过第二掩埋层（130）与第一掩埋层（120）分离，其中内部或外部二极管 148）耦合在第一掩埋层（120）和延伸漏极（108,156）之间以增加击穿电压。

70. 发明申请

US20050253191A1 Robust DEMOS transistors and method for making the same 有权
标题翻译：坚固的DEMOS晶体管及其制造方法
公开(公告)号：US20050253191A1
公开(公告)日：2005-11-17
申请号：US10837918
申请日：2004-05-03
申请人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
发明人： Sameer Pendharkar , Ramanathan Ramani , Taylor Efland
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.
摘要翻译：提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有第一种掺杂剂的浓度高于第二部分。

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