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61. 发明授权

US5856704A Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier 失效
标题翻译：电容器，集成电路，扩散阻挡层以及形成导电扩散阻挡层的方法
公开(公告)号：US5856704A
公开(公告)日：1999-01-05
申请号：US79817
申请日：1998-05-15
申请人： Paul J. Schuele
发明人： Paul J. Schuele
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/92 , H01L23/48 , H01L23/52
CPC分类号： H01L28/40 , H01L27/1085
摘要： A capacitor having a pair of conductive electrodes separated by a dielectric layer and wherein at least one of the electrodes comprise Ti.sub.x Al.sub.1-x N, and wherein the variable "x" lies in a range of about 0.4 to about 0.8. The invention also contemplates a method for forming an electrically conductive diffusion barrier on a silicon substrate and which comprises providing a chemical vapor deposition reactor having a chamber; positioning the silicon substrate in the chemical vapor deposition reactor chamber; providing a source of gaseous titanium aluminum and nitrogen to the chemical vapor deposition reactor chamber; and providing temperature and pressure conditions in the chemical vapor deposition reactor chamber effective to deposit an electrically conductive diffusion barrier layer on the silicon substrate comprising Ti.sub.x Al.sub.1-x N, and wherein the variable "x" is in a range of about 0.4 to about 0.8.
摘要翻译：一种电容器，其具有由电介质层分离的一对导电电极，并且其中至少一个所述电极包括TixAl1-xN，并且其中所述变量“x”在约0.4至约0.8的范围内。本发明还考虑了一种在硅衬底上形成导电扩散阻挡层的方法，该方法包括提供具有室的化学气相沉积反应器; 将硅衬底定位在化学气相沉积反应器室中; 向化学气相沉积反应器室提供气态钛铝和氮源; 以及在化学气相沉积反应器室中提供温度和压力条件，其有效地在包含TixAl1-xN的硅衬底上沉积导电扩散阻挡层，并且其中变量“x”在约0.4至约0.8的范围内。

62. 发明授权

US5808854A Capacitor construction with oxidation barrier blocks 失效
公开(公告)号：US5808854A
公开(公告)日：1998-09-15
申请号：US687248
申请日：1996-07-25
申请人： Thomas A. Figura , Paul J. Schuele
发明人： Thomas A. Figura , Paul J. Schuele
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/06
CPC分类号： H01L27/10852 , H01L28/40
摘要： A capacitor apparatus includes, a) a substrate having a node; b) an inner capacitor plate in ohmic electrical connection with the substrate node; c) an outer capacitor plate; d) a capacitor dielectric layer interposed between inner and outer capacitor plates; e) an electrically conductive reaction barrier layer interposed between the substrate node and the inner capacitor plate, the reaction barrier layer having outer lateral edges which are recessed beneath the inner capacitor plate; and f) oxidation barrier blocks being received over the recessed outer lateral edges beneath the inner capacitor plate. Methods of forming such a capacitor are also disclosed.

63. 发明授权

US5654224A Capacitor construction with oxidation barrier blocks 失效
标题翻译：具有氧化屏障块的电容器结构
公开(公告)号：US5654224A
公开(公告)日：1997-08-05
申请号：US686386
申请日：1996-07-25
申请人： Thomas A. Figura , Paul J. Schuele
发明人： Thomas A. Figura , Paul J. Schuele
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70 , H01G4/06
CPC分类号： H01L27/10852 , H01L28/40
摘要： A method of forming a capacitor apparatus includes providing a substrate having a node, providing an electrically conductive reaction barrier layer with opposed recessed lateral edges over the substrate node, forming an inner capacitor plate, providing oxidation barrier blocks over the opposed recessed lateral edges, forming a dielectric layer and providing an outer capacitor plate.
摘要翻译：一种形成电容器装置的方法包括：提供具有节点的基板，提供导电反应势垒层，该导电反应势垒层在衬底节点上方具有相对的凹入的横向边缘，形成内部电容器板，在相对的凹入侧边缘上提供氧化阻挡块，形成介电层并提供外部电容器板。

64. 发明授权

US5492853A Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device 失效
标题翻译：在形成半导体器件期间使用沟槽和绝缘层形成接触的方法
公开(公告)号：US5492853A
公开(公告)日：1996-02-20
申请号：US209584
申请日：1994-03-11
申请人： Nanseng Jeng , Steven T. Harshfield , Paul J. Schuele
发明人： Nanseng Jeng , Steven T. Harshfield , Paul J. Schuele
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/1082 , H01L27/10873 , Y10S148/014
摘要： A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide. The nitride and oxide is removed from the sidewalls, and a conductive layer is formed over the exposed trench sidewalls, the trench bottom being insulated from the conductive layer by the oxide layer over the bottom of the trench. The oxide on the bottom of the trench contacts the field oxide. The contact is isolated from the substrate along the trench bottom and the second sidewall, making contact with the substrate only in the area of the first sidewall.
摘要翻译：用于在半导体器件上形成与半导体衬底的接触的结构和工艺包括在半导体衬底上和场氧化物区域上形成图案化掩模的步骤，然后蚀刻半导体衬底和场氧化物区域以形成沟槽。沟槽包括底部和由硅组成的第一侧壁和包括场氧化物的第二侧壁。蚀刻步骤去除衬底中的掺杂区域的一部分。接下来，在衬底上形成覆盖氮化物层和覆盖氧化物层，并且在氮化物层和氧化物层上执行衬垫蚀刻，在第一和第二侧壁上留下氮化物和氧化物。沟槽底部被氧化以在沟槽的底部形成一层氧化物，从而使沟槽底部绝缘，并且氧化物侵蚀在侧壁上的氮化物和氧化物之下，以与场氧化物结合。从侧壁去除氮化物和氧化物，并且在暴露的沟槽侧壁上形成导电层，沟槽底部通过沟槽底部的氧化物层与导电层绝缘。沟槽底部的氧化物与场氧化物接触。接触件沿着沟槽底部和第二侧壁与衬底隔离，仅在第一侧壁的区域中与衬底接触。

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