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61. 发明申请

US20110297960A1 TRANSISTOR ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：晶体管组件及其制造方法
公开(公告)号：US20110297960A1
公开(公告)日：2011-12-08
申请号：US13213967
申请日：2011-08-19
申请人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
发明人： Kenichiro Tanaka , Tetsuzo Ueda , Hisayoshi Matsuo , Masahiro Hikita
IPC分类号： H01L21/60 , H01L29/78
CPC分类号： H01L29/7786 , H01L23/053 , H01L23/562 , H01L29/2003 , H01L29/225 , H01L29/452 , H01L29/475 , H01L2224/72 , H01L2924/01079 , H01L2924/12032 , H01L2924/00
摘要： A method for manufacturing a transistor assembly includes the steps of: (a) forming a transistor; (b) polishing a base substrate; and (c) securing the transistor of which the base substrate is polished to a support substrate. The step (a) is a step of forming a first semiconductor layer and a second semiconductor layer on a principle surface of the base substrate. The step (b) is a step of polishing a surface of the base substrate opposite to the principle surface. The step (c) is a step of securing the transistor on the support substrate in the presence of a stress applied on the base substrate in such a direction that a warp of the base substrate is reduced. The base substrate is made of a material different from that of the first semiconductor layer and the second semiconductor layer, and a tensile stress is applied on the second semiconductor layer.
摘要翻译：晶体管组件的制造方法包括以下步骤：（a）形成晶体管; （b）抛光基底; 和（c）将基底基板抛光的晶体管固定到支撑基板上。步骤（a）是在基底基板的主表面上形成第一半导体层和第二半导体层的工序。步骤（b）是对基材的与主面相反的表面进行研磨的工序。步骤（c）是在施加到基底基板上的应力存在下，使晶体管固定在支撑基板上，使基板的翘曲减小的方向。基底由不同于第一半导体层和第二半导体层的材料制成，并且在第二半导体层上施加拉伸应力。

62. 发明授权

US08003975B2 Semiconductor integrated circuit device and method for fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08003975B2
公开(公告)日：2011-08-23
申请号：US11600101
申请日：2006-11-16
申请人： Tetsuzo Ueda , Tsuyoshi Tanaka
发明人： Tetsuzo Ueda , Tsuyoshi Tanaka
IPC分类号： H01L31/00
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/66 , H01L29/2003 , H01L29/4175 , H01L29/7787 , H01L2221/6835 , H01L2223/6627 , H01L2924/0002 , H01L2924/14 , H01L2924/19032 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a first interconnection formed on the semiconductor layer through the first through hole and connected to one of the source electrode, the drain electrode and the gate electrode which is exposed in the first through hole; and a second interconnection formed on the insulating film through the second through hole and connected to another of the source electrode, the drain electrode and the gate electrode which is exposed in the second through hole. The first interconnection and the second interconnection face each other and form a microstrip line.
摘要翻译：半导体集成电路器件包括：半导体层，其主表面上形成有源电极，漏电极和栅电极，并具有第一通孔; 形成为与所述半导体层接触并具有第二通孔的绝缘膜; 通过所述第一通孔形成在所述半导体层上并与所述第一通孔露出的所述源电极，所述漏电极和所述栅电极之一连接的第一互连; 以及通过第二通孔形成在绝缘膜上的第二互连，并与第二通孔中露出的源电极，漏电极和栅电极中的另一个连接。第一互连和第二互连彼此面对并形成微带线。

63. 发明授权

US07898002B2 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译：氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

64. 发明授权

US07863649B2 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07863649B2
公开(公告)日：2011-01-04
申请号：US12331668
申请日：2008-12-10
申请人： Masahiro Hikita , Tetsuzo Ueda
发明人： Masahiro Hikita , Tetsuzo Ueda
IPC分类号： H01L29/739
CPC分类号： H01L29/2003 , H01L29/1066 , H01L29/42316 , H01L29/7786 , H01L29/808
摘要： A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.
摘要翻译：氮化物半导体器件包括：顺序地在衬底上形成的第一至第三氮化物半导体层。第二氮化物半导体层的带隙能量大于第一氮化物半导体层的带隙能量。第三氮化物半导体层具有开口。形成p型第四氮化物半导体层，使得开口被填充。在第四氮化物半导体层上形成栅电极。

65. 发明申请

US20100327293A1 FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

66. 发明授权

US07859087B2 Semiconductor device 有权
公开(公告)号：US07859087B2
公开(公告)日：2010-12-28
申请号：US12637240
申请日：2009-12-14
申请人： Tomohiro Murata , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tomohiro Murata , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L23/58
CPC分类号： H01L29/7787 , H01L23/367 , H01L23/3677 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

67. 发明授权

US07728359B2 Nitride semiconductor based bipolar transistor and the method of manufacture thereof 有权
标题翻译：氮化物半导体双极晶体管及其制造方法
公开(公告)号：US07728359B2
公开(公告)日：2010-06-01
申请号：US11812591
申请日：2007-06-20
申请人： Tatsuo Morita , Tetsuzo Ueda
发明人： Tatsuo Morita , Tetsuzo Ueda
IPC分类号： H01L51/00
CPC分类号： H01L29/2003 , H01L29/201 , H01L29/66318 , H01L29/7371
摘要： In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.
摘要翻译：在基于氮化物半导体的双极型晶体管中，形成为与发射极层接触的接触层由n型InAlGaN四元混晶构成，选择性地去除发射极层和接触层，使得其上形成有发射极的势垒高度例如，在InAlGaN四元混晶中的欧姆电极接触电阻可以降低，使得WSi发射极成为檐。通过使用发射电极作为掩模的自对准工艺形成基极。通过这样的结构，能够充分地缩短发射极与基极的边缘之间的距离，能够降低基极电阻。结果，可以实现具有良好的高频特性的双极晶体管。

68. 发明授权

US07700392B2 Manufacturing method of semiconductor laser devices and manufacturing apparatus of the same 失效
标题翻译：半导体激光装置的制造方法及其制造装置
公开(公告)号：US07700392B2
公开(公告)日：2010-04-20
申请号：US11286348
申请日：2005-11-25
申请人： Tetsuzo Ueda , Hisanori Ishiguro
发明人： Tetsuzo Ueda , Hisanori Ishiguro
IPC分类号： H01L21/78 , H01L21/301 , H01L21/46
CPC分类号： H01L21/67213 , B82Y20/00 , H01L21/67132 , H01S5/0201 , H01S5/0202 , H01S5/0213 , H01S5/028 , H01S5/34333
摘要： The present invention is to provide a semiconductor laser device manufacturing method for realizing highly reliable semiconductor laser devices. The semiconductor laser device manufacturing method includes: cutting a wafer into bar-shaped wafers by scanning an electron beam on the front side of the wafer on which a semiconductor laser structure has been formed so as to cause cracks which trigger the cutting of the wafer; and depositing front and back coating films on the end faces, which have been newly exposed by the cutting of the wafer, of the cut wafers. In the method the cut wafers are transferred in a non-ambient atmosphere at a time between the cutting of the wafer and the depositing of the end face coating films.
摘要翻译：本发明提供一种实现高可靠性的半导体激光器件的半导体激光器件制造方法。半导体激光器件制造方法包括：通过扫描在其上形成有半导体激光器结构的晶片的正面上的电子束来将晶片切割成棒状晶片，以引起触发切割晶片的裂纹; 并且通过切割晶片新近暴露的端面上沉积切割晶片的前后涂膜。在该方法中，切割晶片在切割晶片和沉积端面涂膜之间的时间在非环境大气中转移。

69. 发明申请

US20100090250A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100090250A1
公开(公告)日：2010-04-15
申请号：US12637240
申请日：2009-12-14
申请人： Tomohiro MURATA , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tomohiro MURATA , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/205 , H01L29/772 , H01L29/06
CPC分类号： H01L29/7787 , H01L23/367 , H01L23/3677 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
摘要翻译：半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。钝化膜包括由氮化铝制成的第一子膜。

70. 发明申请

US20090121775A1 TRANSISTOR AND METHOD FOR OPERATING THE SAME 有权
标题翻译：晶体管及其操作方法
公开(公告)号：US20090121775A1
公开(公告)日：2009-05-14
申请号：US11995040
申请日：2006-06-27
申请人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
发明人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
IPC分类号： H01L29/207 , H03K17/687
CPC分类号： H01L29/739 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7786
摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
摘要翻译：在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压，孔被注入到通道中以增加在通道中流动的电流。

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