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    • 68. 发明授权
    • Wave-shaping circuit
    • 波形整形电路
    • US4574206A
    • 1986-03-04
    • US300604
    • 1981-09-09
    • Shigeru TodokoroTadashi Kojima
    • Shigeru TodokoroTadashi Kojima
    • H03K5/131G11B5/09G11B20/10H03K5/08H04L25/03H04L25/08H03K5/135
    • H03K5/084
    • A wave-shaping circuit which comprises a comparator for comparing the level of a signal reproduced from a magnetic tape on which, for example, PCM signals are recorded with the level of a reference signal, and a D flip-flop circuit for holding an output signal from the comparator for a prescribed period. Where the reproduced signal has a higher level than the original level of the reference signal, then the reference signal is made to have a higher level than the original level by an output signal from the D flip-flop circuit, that is, an output signal from the comparator. Where the reproduced signal has a lower level than the original level of a reference signal, then the reference signal is made to have a lower level than the original level by the output signal from the comparator. As a result, strains occurring at the high density recording are not reproduced.
    • 一种波形整形电路,包括比较器,用于比较从其上记录有例如PCM信号的磁带再现的信号的电平与用于保持输出的D触发器电路 来自比较器的指定时间的信号。 在再现信号具有比参考信号的原始电平更高的电平的情况下,通过来自D触发器电路的输出信号,使参考信号具有比原始电平更高的电平,即,输出信号 从比较。 在再现信号具有比参考信号的原始电平低的电平的情况下,通过比较器的输出信号使参考信号具有比原始电平更低的电平。 结果,不再现在高密度记录下出现的应变。
    • 69. 发明授权
    • Error correcting system
    • 纠错系统
    • US4498175A
    • 1985-02-05
    • US430002
    • 1982-09-30
    • Masahide NagumoJun InagawaTadashi Kojima
    • Masahide NagumoJun InagawaTadashi Kojima
    • G06F11/10G06F7/72G11B7/00G11B7/004G11B20/18H03M13/00H03M13/15
    • H03M13/151G06F7/724G06F7/726G11B20/1809
    • An error correcting system uses an error location polynomial which is defined by double correction BCH codes each consisting of the elements of a Galois field GF(2.sup.m), and thereby generates error locations .sigma..sub.1 and .alpha..sup.2 and error patterns e.sub.1 and 2.sub.2. The system has a first data processing system for performing only addition and multiplication to generate the error locations .sigma..sub.1 and .alpha..sup.2, and a second data processing system for performing only addition and multiplication to generate the error patterns e.sub.1 and 2.sub.2. The first data processing system comprises a syndrome generator, a memory, an arithmetic logic unit, registers, latch circuits, registers, adder circuits and a zero detector. The second data processing system comprises a gate circuit, latch circuits, an arithmetic logic unit, and the registers of a memory.
    • 误差校正系统使用错误位置多项式,该多项式由由Galois域GF(2m)的元素组成的双校正BCH码定义,从而产生误差位置sigma1和α2以及误差模式e1和22。 具有用于仅执行加法和乘法以产生错误位置sigma1和alpha2的第一数据处理系统,以及仅执行相加和相乘以产生错误模式e1和22的第二数据处理系统。第一数据处理系统包括 校正子发生器,存储器,算术逻辑单元,寄存器,锁存电路,寄存器,加法器电路和零检测器。 第二数据处理系统包括门电路,锁存电路,算术逻辑单元和存储器的寄存器。