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    • 61. 发明授权
    • Mantissa processing circuit of floating point arithmetic apparatus for
addition and subtraction
    • 用于加法和减法的浮点运算装置的尾数处理电路
    • US5200916A
    • 1993-04-06
    • US813664
    • 1991-12-27
    • Tadahiro Yoshida
    • Tadahiro Yoshida
    • G06F7/00G06F5/01G06F7/38G06F7/485G06F7/50G06F7/76
    • G06F7/485G06F5/012G06F7/49947
    • A mantissa processing circuit of a floating point arithmetic apparatus defines an arithmetic unit 11, a rounding adder 12, a postshift-count-encode circuit (PSCE circuit) 13, and a postshift circuit 14. The arithmetic unit 11 outputs as a first intermediate result (intermediate sum) R1 the results of addition and subtraction on preshifted mantissa data ma and mb. The rounding adder 12 outputs as a second intermediate result (rounding result) R2 the result of rounding addition for the intermediate sum R1. The PSCE circuit 13 outputs data on postshift to be applied to the rounding result R2. The postshift circuit 14 actually shifts the rounding result R2 to the right or left for normalization. The PSCE circuit 13 includes a shifting part 15 and a shift correcting part 16. The shifting part 15 specifies the contents of postshift according to the position of the first non-zero value bit in the intermediate sum R1. The shift correcting part 16 corrects the quantity of postshift when it is expected that the position of the first non-zero value bit is moved for a carry at the time of rounding addition. The rounding adder 12 and the PSCE circuit 13 execute processing in parallel, so that there can be enhanced the processing speeds of the rounding and normalization for the results of addition and subtraction on the mantissa data ma and mb.
    • 浮点算术装置的尾数处理电路定义了运算单元11,舍入加法器12,后移计数编码电路(PSCE电路)13和后移电路14.算术单元11作为第一中间结果输出 (中和)R1对预定尾数数据ma和mb的加法和减法结果。 舍入加法器12作为第二中间结果(舍入结果)R2输出中间和R1的舍入加法结果。 PSCE电路13输出用于换档的数据,以应用于舍入结果R2。 换档电路14实际上将舍入结果R2向右或向左移动以进行归一化。 PSCE电路13包括移位部15和移位校正部16.移位部15根据中间和R1中的第一非零值位的位置来指定副移位的内容。 当预期在舍入加法时,第一非零值位的位置为进位而移动时,换档校正部16校正换挡量。 舍入加法器12和PSCE电路13并行执行处理,从而可以提高对尾数数据ma和mb的加法和减法结果的舍入和归一化的处理速度。
    • 64. 发明授权
    • Start-stop synchronous data transmission system with a reduced redundancy
    • 起停同步数据传输系统冗余减少
    • US4635248A
    • 1987-01-06
    • US700294
    • 1985-02-11
    • Tadahiro Yoshida
    • Tadahiro Yoshida
    • H04J3/24H04B1/66H04L5/24H04J3/00
    • H04L5/24
    • Data signals in each channel over a plurality of sequential frames of a time division multiplex signal as received are temporarily stored in each channel memory, and are read out together from the channel memory at a given time to form a combined data signal. A start bit signal, a stop bit signal and an address signal corresponding to the channel are added to the combined data signal to form a start-stop synchronous fresh channel signal. The resultant N fresh channels are sequentially sent out to a common transmission line as a fresh time division multiplex signal with a reduced redundancy. A plurality of sub-equipments are connected to the common transmission line and take into the data signals of a channel assigned thereto according to the address data signal.
    • 接收到的时分多路复用信号的多个顺序帧中的每个信道中的数据信号被临时存储在每个通道存储器中,并且在给定时间从通道存储器一起读出以形成组合的数据信号。 将起始位信号,停止位信号和对应于该通道的地址信号加到组合数据信号上以形成起始 - 停止同步新信道信号。 所得N个新鲜信道被顺序地发送到公共传输线路,作为具有减少的冗余度的新的时分多路复用信号。 多个子设备连接到公共传输线,并根据地址数据信号接收分配给它的信道的数据信号。