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61. 发明申请

US20100052058A1 DOWNSIZE POLYSILICON HEIGHT FOR POLYSILICON RESISTOR INTEGRATION OF REPLACEMENT GATE PROCESS 有权
标题翻译：多晶硅电阻多晶硅高分子聚合过程
公开(公告)号：US20100052058A1
公开(公告)日：2010-03-04
申请号：US12401876
申请日：2009-03-11
申请人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0629 , H01L21/82345 , H01L27/088 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.
摘要翻译：公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

62. 发明申请

US20100022061A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20100022061A1
公开(公告)日：2010-01-28
申请号：US12179395
申请日：2008-07-24
申请人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

63. 发明申请

US20090286384A1 Dishing-free gap-filling with multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US20090286384A1
公开(公告)日：2009-11-19
申请号：US12152380
申请日：2008-05-14
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/306 , H01L21/283 , H01L21/20 , H01L21/461 , H01L21/302
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

64. 发明申请

US20090273055A1 Fuse Structure 有权
标题翻译：保险丝结构
公开(公告)号：US20090273055A1
公开(公告)日：2009-11-05
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

65. 发明申请

US20080179688A1 Method and Apparatus for Semiconductor Device with Improved Source/Drain Junctions 有权
标题翻译：具有改进的源极/漏极结的半导体器件的方法和装置
公开(公告)号：US20080179688A1
公开(公告)日：2008-07-31
申请号：US12058997
申请日：2008-03-31
申请人： Kong Beng Thei , Chung Long Cheng , Harry Chuang
发明人： Kong Beng Thei , Chung Long Cheng , Harry Chuang
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/1083 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
摘要翻译：公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

66. 发明申请

US20080054250A1 Structure and methods for forming SiGe stressors 有权
标题翻译：形成SiGe应激物的结构和方法
公开(公告)号：US20080054250A1
公开(公告)日：2008-03-06
申请号：US11602100
申请日：2006-11-20
申请人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
发明人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 应力源，其具有至少一部分在所述半导体衬底中并且邻近所述栅叠层，其中所述应力源包括第一导电类型的杂质; 所述半导体衬底的与所述应力源相邻的部分以及所述应力源与所述栅极堆叠相反的一侧，其中所述半导体衬底的所述部分掺杂有所述第一导电类型的杂质。

67. 发明授权

US07298011B2 Semiconductor device with recessed L-shaped spacer and method of fabricating the same 有权
标题翻译：具有凹形L形间隔件的半导体器件及其制造方法
公开(公告)号：US07298011B2
公开(公告)日：2007-11-20
申请号：US11215103
申请日：2005-08-30
申请人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
IPC分类号： H01L29/94
CPC分类号： H01L29/6656 , H01L21/28052 , H01L21/76897 , H01L29/66507 , H01L29/6653
摘要： A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.
摘要翻译：具有凹入的L形间隔物的半导体器件及其制造方法。凹进的L形间隔件包括垂直部分和水平部分。垂直部分设置在导体图案的下侧壁上，露出其上侧壁。顶部间隔物在L形间隔件上，其中L形间隔件的垂直部分与顶部间隔物的宽度比为至少约2:1。

68. 发明申请

US20050285222A1 New fuse structure 审中-公开
标题翻译：新的保险丝结构
公开(公告)号：US20050285222A1
公开(公告)日：2005-12-29
申请号：US11137075
申请日：2005-05-25
申请人： Kong-Beng Thei , Chung Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L23/525 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

69. 发明授权

US08981562B2 Wiring layout having differently shaped vias 有权
标题翻译：接线布局具有不同形状的通孔
公开(公告)号：US08981562B2
公开(公告)日：2015-03-17
申请号：US12134381
申请日：2008-06-06
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： H01L21/00 , G03F1/00 , G03F1/36 , H01L21/768 , H01L21/311
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

70. 发明授权

US08735235B2 Integrated circuit metal gate structure and method of fabrication 有权
标题翻译：集成电路金属栅极结构及其制造方法
公开(公告)号：US08735235B2
公开(公告)日：2014-05-27
申请号：US12276015
申请日：2008-11-21
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
IPC分类号： H01L21/338
CPC分类号： H01L29/78 , H01L21/28114 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/7833
摘要： A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.
摘要翻译：提供一种使用门最后工艺形成金属栅的方法。在基板上形成沟槽。沟槽的轮廓被修改以在沟槽的孔处提供第一宽度，并且在沟槽的底部提供第二宽度。轮廓可以通过包括锥形侧壁形成。金属栅极可以形成在具有改变的轮廓的沟槽中。还提供了一种半导体器件，其包括在栅极顶部具有比栅极的底部更大的宽度的栅极结构。

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