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    • 61. 发明授权
    • Memory board with self-testing capability
    • 内存板具有自检功能
    • US08359501B1
    • 2013-01-22
    • US13183253
    • 2011-07-14
    • Hyun LeeJayesh R. BhaktaSoonju Choi
    • Hyun LeeJayesh R. BhaktaSoonju Choi
    • G11C29/00
    • G11C29/12G11C5/04
    • A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.
    • 自检存储器模块包括被配置为可操作地耦合到计算机系统的存储器控​​制器的印刷电路板,并且在印刷电路板上包括多个存储器件,多个存储器件中的每个存储器件包括数据,地址 和控制端口。 存储器模块还包括被配置为产生用于测试存储器件的地址和控制信号的控制模块。 存储器模块包括包括多个数据处理器的数据模块。 每个数据处理程序可独立于多个数据处理程序中的每个其他数据处理程序操作。 每个数据处理器可操作地耦合到一个或多个存储器件的对应的多个数据端口,并且被配置为产生用于写入对应的多个数据端口的数据。
    • 68. 发明申请
    • METHOD AND APPARATUS FOR OPTIMIZING DRIVER LOAD IN A MEMORY PACKAGE
    • 用于在存储器包中优化驱动器负载的方法和装置
    • US20120106228A1
    • 2012-05-03
    • US13288850
    • 2011-11-03
    • Hyun Lee
    • Hyun Lee
    • G11C5/06G11C8/06H01L21/768
    • G11C5/066G11C5/06G11C7/1057G11C7/1084G11C7/12
    • An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.
    • 提供一种包括多个阵列管芯和至少两个管芯互连的装置。 第一管芯互连与第一阵列管芯的数据端口和第二阵列管芯的数据端口电连通,并且不与第三阵列管芯的数据端口电连通。 第二管芯互连与第三阵列管芯的数据端口电连通,并且不与第一阵列管芯和第二阵列管芯的数据端口电连通。 该装置包括控制管芯,该控制管芯包括被配置为将数据信号传送到第一管芯互连而不是第二管芯互连的第一数据管道,以及至少第二数据管道,其被配置为将数据信号传输到第二管芯互连和 不是第一个芯片互连。