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61. 发明授权

US07768009B2 Display device and manufacturing method of the same 有权
标题翻译：显示装置及其制造方法相同
公开(公告)号：US07768009B2
公开(公告)日：2010-08-03
申请号：US12196798
申请日：2008-08-22
申请人： Satoshi Kobayashi , Ikuko Kawamata , Koji Dairiki , Shigeki Komori , Toshiyuki Isa , Shunpei Yamazaki
发明人： Satoshi Kobayashi , Ikuko Kawamata , Koji Dairiki , Shigeki Komori , Toshiyuki Isa , Shunpei Yamazaki
IPC分类号： H01L29/04 , H01L29/10 , H01L27/12
CPC分类号： H01L29/04 , H01L29/41733 , H01L29/4908 , H01L29/66765 , H01L29/78696
摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.
摘要翻译：一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

62. 发明申请

US20090224249A1 Method For Manufacturing EL Display Device 有权
标题翻译：制造EL显示装置的方法
公开(公告)号：US20090224249A1
公开(公告)日：2009-09-10
申请号：US12390264
申请日：2009-02-20
申请人： Hidekazu Miyairi , Shigeki Komori , Toshiyuki Isa , Atsushi Umezaki
发明人： Hidekazu Miyairi , Shigeki Komori , Toshiyuki Isa , Atsushi Umezaki
IPC分类号： H01L29/04 , H01L21/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/3262
摘要： A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.
摘要翻译：安装在EL显示装置上的薄膜晶体管的制造工艺简化。通过堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜来制造薄膜晶体管; 在堆叠的膜上形成第一抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 在薄膜堆叠体上进行侧蚀刻进行第二蚀刻，形成栅电极层; 以及使用第二抗蚀剂掩模形成源极和漏极电极层等。使用薄膜晶体管制造EL显示装置。

63. 发明授权

US07396764B2 Manufacturing method for forming all regions of the gate electrode silicided 失效
标题翻译：用于形成栅电极的所有区域的制造方法被硅化
公开(公告)号：US07396764B2
公开(公告)日：2008-07-08
申请号：US11381654
申请日：2006-05-04
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： H01L21/44
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/28518 , H01L21/823835 , H01L21/82385 , H01L29/4975 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered.A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.
摘要翻译：提供了可以提高栅电极的所有区域被硅化的MOS晶体管的性能的技术。将nMOS晶体管的栅极绝缘膜和栅电极依次层叠并形成在半导体基板上。 nMOS晶体管的源极/漏极区域形成在半导体衬底的上表面中。在硅化栅电极的所有区域之后，源极/漏极区域被硅化。因此，通过在栅极电极的硅化后硅化硅化源极/漏极区域，通过在栅电极的硅化处理进行热处理，硅化物不会在源极/漏极区域内固定。因此，源极/漏极区域的电阻减小，结点泄漏可以减小。结果，提高了nMOS晶体管的性能。

64. 发明授权

US06844228B2 Manufacturing method of a semiconductor device capable of accurately setting a resistance value of a resistance element 失效
标题翻译：能够精确地设定电阻元件的电阻值的半导体器件的制造方法
公开(公告)号：US06844228B2
公开(公告)日：2005-01-18
申请号：US10700770
申请日：2003-11-05
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L21/8244
CPC分类号： H01L27/0629
摘要： A photoresist (6) is formed on an element isolation insulating film (2) so as to cover the upper and side surfaces of a polysilicon film (4R) which functions as a resistance element. With the photoresist (6) as an implantation mask, n-type impurities (7) such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (1). The dose is in the order of 1013/cm2. Through this processing, an LDD region (8) of MOSFET is formed inside the upper surface of the silicon substrate (1) within a transistor forming region. The impurities (7) are also implanted in a polysilicon film (4G). On the other hand, as the polysilicon film (4R) is covered by the photoresist (6), the impurities (7) are not implanted into the polysilicon film (4R).
摘要翻译：在元件隔离绝缘膜（2）上形成光致抗蚀剂（6），以覆盖用作电阻元件的多晶硅膜（4R）的上表面和侧表面。以光致抗蚀剂（6）作为注入掩模，从大致垂直于硅衬底（1）的上表面的方向离子注入诸如磷的n型杂质（7）。剂量为10 13 / cm 2的数量级。通过这种处理，在晶体管形成区域内的硅衬底（1）的上表面内形成有MOSFET的LDD区域（8）。杂质（7）也被植入多晶硅膜（4G）中。另一方面，由于多晶硅膜（4R）被光致抗蚀剂（6）覆盖，杂质（7）不被注入到多晶硅膜（4R）中。

65. 发明授权

US06552926B2 Magnetic random-access memory 失效
公开(公告)号：US06552926B2
公开(公告)日：2003-04-22
申请号：US10096878
申请日：2002-03-14
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： G11C1100
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/16 , H01L27/224
摘要： A magnetic random-access memory comprises a semiconductor substrate (1) on which write word lines (2) and bit lines (3) intersecting each other are arranged, TMR elements (7) formed individually in areas of intersection of the write word lines (2) and the bit lines (3), each TMR element (7) being formed by stacking a free-spin layer (4) whose magnetization direction is variable, a fixed-spin layer (6) whose magnetization direction is fixed and an insulator layer (5) placed between the first and second magnetic substance layers, and access transistors (10). The TMR elements (7) are located where word lines (8a) which serve as gates of the access transistors (10) intersect the bit lines (3) so that the word lines (8a) perform the functions of both write and read word lines. This arrangement reduces the complexity involved in creating a multilayer interconnection structure, simplifies the structure and manufacturing processes of the magnetic random-access memory, and enables its miniaturization and a higher level of integration.

66. 发明授权

US06492674B1 Semiconductor device having an improved plug structure and method of manufacturing the same 失效
标题翻译：具有改进的插塞结构的半导体器件及其制造方法
公开(公告)号：US06492674B1
公开(公告)日：2002-12-10
申请号：US09584690
申请日：2000-06-01
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： H01L31119
CPC分类号： H01L21/823475 , H01L21/76838 , H01L21/823481 , H01L2924/0002 , H01L2924/00
摘要： A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects a pair of active regions of the semiconductor elements formed on the different sides of the isolating layer. Alternatively, a conductive plug is formed in an interlayer insulation film and on a conducive line formed on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects the conductive line and an active region of the semiconductor element.
摘要翻译：在层间绝缘膜和隔离半导体衬底上的半导体元件的隔离层上形成导电插塞。导电插塞电连接形成在隔离层的不同侧上的半导体元件的一对有源区域。或者，导电插塞形成在层间绝缘膜中，并且形成在隔离半导体衬底上的半导体元件的隔离层上的导电线上。导电插头电连接导线和半导体元件的有源区。

67. 发明授权

US06452246B1 Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device 有权
标题翻译：具有改进的隔离结构的半导体器件以及半导体器件的制造方法
公开(公告)号：US06452246B1
公开(公告)日：2002-09-17
申请号：US09514944
申请日：2000-02-28
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： H01L2900
CPC分类号： H01L21/76232
摘要： A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At least a portion of the surface of the trench material adjoining the semiconductor substrate is depressed by a predetermined depth with reference to the primary surface of the semiconductor device. Thus, prevented is a decrease in a drain current of a semiconductor device having a trench isolation structure.
摘要翻译：在半导体衬底的主表面上形成沟槽，并且填充沟槽材料以将半导体衬底的表面区域分离成多个有源区域。与半导体衬底相邻的沟槽材料的表面的至少一部分相对于半导体器件的主表面被压下预定的深度。因此，防止了具有沟槽隔离结构的半导体器件的漏极电流的减小。

68. 发明授权

US06448630B1 Semiconductor device comprising a polish preventing pattern 失效
标题翻译：包括防抛光图案的半导体器件
公开(公告)号：US06448630B1
公开(公告)日：2002-09-10
申请号：US09292383
申请日：1999-04-15
申请人： Shigeki Komori
发明人： Shigeki Komori
IPC分类号： H01L2176
CPC分类号： H01L23/564 , H01L21/31053 , H01L21/76229 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element formation region, a loop-shaped element formation region dummy is formed in a uniform width and at a uniform distance from the edge of the element formation region to have a loop shape. That can prevent formation of such a portion that is on a line extended from a gap between polish preventing patterns as well as a large gap between an element formation region and a polish preventing pattern. Accordingly, local application of large pressure to an end of an element formation region is suppressed which is caused when a polishing cloth bends. As a result, the semiconductor device does not have a locally substantially etched portion. The planarity of the surface of an element formation region is maintained in the semiconductor device.
摘要翻译：提供了具有可以提高CMP方法研磨之后的元件形成区域的平坦度的防抛光图案的半导体器件。对于元件形成区域的形状，环形元件形成区域虚拟部以与元件形成区域的边缘相同的宽度和均匀的距离形成为环形。这可以防止在防止防波纹图案之间的间隙延伸的线上形成这样的部分，以及元件形成区域和抛光防止图案之间的大间隙。因此，当抛光布弯曲时，局部地施加大的压力到元件形成区域的端部。结果，半导体器件不具有局部基本上蚀刻的部分。元件形成区域的表面的平面度保持在半导体器件中。

69. 发明授权

US5978294A Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method 失效
标题翻译：存储单元评估半导体器件，其制造方法和存储单元评估方法
公开(公告)号：US5978294A
公开(公告)日：1999-11-02
申请号：US112506
申请日：1998-07-09
申请人： Shuichi Ueno , Tomohiro Yamashita , Hidekazu Oda , Shigeki Komori
发明人： Shuichi Ueno , Tomohiro Yamashita , Hidekazu Oda , Shigeki Komori
IPC分类号： G01R31/28 , G11C7/14 , G11C11/401 , G11C11/406 , G11C29/12 , G11C29/24 , H01L21/66 , H01L21/8242 , H01L27/108 , G11C7/02 , G11C11/24
CPC分类号： G11C7/14 , G11C11/406 , G11C29/24
摘要： A dummy cell part includes a capacitor having a first end which is connected to one of a plurality of pads and a P-N junction element having a first end which is connected to one of the plurality of pads and a second end which is connected to one of the plurality of pads . A sense part is connected to a second end of the capacitor , for sensing a potential on the second end of the capacitor and outputting the result of sensing to one of the plurality of pads . Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.
摘要翻译：虚设单元部分31包括具有连接到多个焊盘<2>中的一个的第一端的电容器<311>和具有连接到多个焊盘中的一个的第一端的PN结元件<312> 的焊盘<2>和连接到多个焊盘<2>之一的第二端。感测部分<32>连接到电容器<311>的第二端，用于感测电容器<311>的第二端上的电位，并将感测结果输出到多个焊盘<2>之一。因此，可以获得能够评估单个存储单元的存储单元评估半导体器件，其制造方法和存储单元评估方法。

70. 发明授权

US5852327A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5852327A
公开(公告)日：1998-12-22
申请号：US709592
申请日：1996-09-09
申请人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
发明人： Shigeki Komori , Tomohiko Yamashita , Masahide Inuishi
IPC分类号： H01L21/768 , H01L23/48 , H01L29/78
CPC分类号： H01L21/74
摘要： In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.
摘要翻译：在半导体器件的半导体衬底中，形成与衬底相同导电类型的多个杂质层。相反导电类型的杂质区域从半导体衬底的主表面穿透至少一个杂质层至一定的深度。杂质区域的底表面在杂质浓度较低的杂质层之间终止。接触导体从杂质区域引出。

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