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61. 发明授权

US07009231B2 Single-phase c-axis doped PGO ferroelectric thin films 有权
标题翻译：单相c轴掺杂PGO铁电薄膜
公开(公告)号：US07009231B2
公开(公告)日：2006-03-07
申请号：US11046620
申请日：2005-01-28
申请人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Wei-Wei Zhuang , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： H01L29/94
CPC分类号： H01L21/31691 , H01L28/55 , H01L41/317
摘要： A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.
摘要翻译：描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括在0.1N和0.5之间的范围内沉积掺杂的前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

62. 发明授权

US06998661B2 Integrated circuit structure including electrodes with PGO ferroelectric thin film thereon 失效
标题翻译：集成电路结构，其中包括具有PGO铁电薄膜的电极
公开(公告)号：US06998661B2
公开(公告)日：2006-02-14
申请号：US10385009
申请日：2003-03-10
申请人： Fengyan Zhang , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/1136 , H01L31/119
CPC分类号： H01L28/65 , C23C16/40 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75 , Y10T428/24917 , Y10T428/2495
摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.
摘要翻译：一种在其上形成电极和铁电薄膜的方法，包括制备基板; 在所述基板上沉积电极，其中所述电极由从由铱和铱复合材料组成的材料组取得的材料形成; 并在其上形成单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。集成电路包括基板; 沉积在所述基底上的电极，其中所述电极由从由铱和铱复合物组成的材料组中取得的材料形成，其中所述铱复合材料取自由IrO 2 ，Ir-Ta-O，Ir-Ti-O，Ir-Nb-O，Ir-Al-O，Ir-Hf-O，Ir-VO，Ir-Zr-O和Ir-O; 以及形成在电极上的单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。

63. 发明授权

US06991942B1 MFIS ferroelectric memory array on SOI and method of making same 失效
标题翻译： SOI上的MFIS铁电存储阵列及其制作方法
公开(公告)号：US06991942B1
公开(公告)日：2006-01-31
申请号：US10953912
申请日：2004-09-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L21/00
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

64. 发明授权

US06972238B2 Oxygen content system and method for controlling memory resistance properties 有权
标题翻译：氧含量系统和控制记忆电阻性质的方法
公开(公告)号：US06972238B2
公开(公告)日：2005-12-06
申请号：US10442628
申请日：2003-05-21
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L27/01 , H01L45/00 , H01L49/00 , H01L21/20
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/016 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.
摘要翻译：提供了一种用于控制存储材料中的电阻特性的存储单元和方法。该方法包括：形成亚锰酸盐; 在氧气氛中退火亚锰矿; 响应于退火控制亚锰矿中的氧含量; 并且响应于氧含量控制亚锰酸盐的电阻。亚锰酸盐是具有通式为RE 1-x X x MnO y y y的钙钛矿型锰氧化物，其中RE是稀土离子， AE是碱土离子，x在0.1和0.5之间。控制亚锰矿中的氧含量包括形成y大于3的富氧RE 1-x A x M x Mn O y Y y区域。低电阻导致富氧亚锰酸盐区域。当y小于3时，形成高电阻。更具体地，该方法形成了邻近缺氧高阻力亚锰酸盐区域的低阻力富氧亚锰酸盐区域。

65. 发明授权

US06955992B2 One mask PT/PCMO/PT stack etching process for RRAM applications 有权
公开(公告)号：US06955992B2
公开(公告)日：2005-10-18
申请号：US10677008
申请日：2003-09-30
申请人： Fengyan Zhang , Sheng Teng Hsu
发明人： Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/28 , G11C13/00 , H01L21/02 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L45/00 , H01L21/302 , H01L21/461
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31122 , H01L21/32136 , H01L27/101 , H01L28/55 , H01L28/65 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.

66. 发明授权

US06849564B2 1R1D R-RAM array with floating p-well 有权
标题翻译： 1R1D具有浮动p-well的R-RAM阵列
公开(公告)号：US06849564B2
公开(公告)日：2005-02-01
申请号：US10376796
申请日：2003-02-27
申请人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang , Fengyan Zhang
IPC分类号： G11C13/00 , H01L27/10 , H01L27/24 , H01L21/00
CPC分类号： H01L27/24 , G11C13/0007 , G11C2213/31 , G11C2213/72 , H01L27/10
摘要： A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; forming n-doped silicon sidewalls overlying the buried n layer; forming a p-doped well of silicon (p-well) overlying the buried n layer; and, forming a 1R1D R-RAM array overlying the p-well. Typically, the combination of the buried n layer and the n-doped sidewalls form an n-doped well (n-well) of silicon. Then, the p-well is formed inside the n-well. In other aspects, the p-well has sidewalls, and the method further comprises: forming an oxide insulator overlying the p-well sidewalls, between the n-well and the R-RAM array.
摘要翻译：提供具有浮动p-well的低电容单电阻/单二极管（1R1D）R-RAM阵列。该制造方法包括：形成集成电路（IC）衬底; 形成覆盖在衬底上的硅的n掺杂掩埋层（n层）; 形成覆盖掩埋n层的n掺杂硅侧壁; 形成覆盖在掩埋n层上的硅（p阱）的p掺杂阱; 并且形成覆盖p阱的1R1D R-RAM阵列。通常，掩埋n层和n掺杂侧壁的组合形成硅的n掺杂阱（n阱）。然后，p阱形成在n阱内。在其他方面，p阱具有侧壁，并且该方法还包括：在n阱和R-RAM阵列之间形成覆盖p阱侧壁的氧化物绝缘体。

67. 发明授权

US06737693B2 Ferroelastic integrated circuit device 失效
标题翻译：铁磁集成电路器件
公开(公告)号：US06737693B2
公开(公告)日：2004-05-18
申请号：US10412890
申请日：2003-04-14
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2976
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

68. 发明授权

US06703655B2 Ferroelectric memory transistor 失效
标题翻译：铁电存储晶体管
公开(公告)号：US06703655B2
公开(公告)日：2004-03-09
申请号：US10385038
申请日：2003-03-10
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2976
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/11502 , H01L29/78391
摘要： A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack. A method of forming a ferroelectric memory transistor includes preparing a substrate, including forming active regions and an oxide device isolation region; forming a gate placeholder structure in a gate region; removing the gate placeholder structure forming a gate void in the gate region; depositing a high-k insulator layer over the structure and in the gate void to from a high-k cup; filling the high-k cup with a ferroelectric material to form a ferroelectric element; depositing a high-k upper insulator layer and removing excess high-k material to form a high-k cap over the ferroelectric element; depositing a top electrode over the high-k cap to form a gate electrode and gate stack; depositing a layer of passivation oxide over the structure; etching the passivation oxide to from contact vias to the active regions and the gate stack; and metallizing the structure to complete the ferroelectric memory transistor.
摘要翻译：铁电存储晶体管包括其中具有有源区的衬底; 包括：高k绝缘体元件，包括高k杯和高k帽; 铁电元件，其中所述铁电元件封装在所述高k绝缘体元件内; 以及位于所述高k绝缘体的顶部上的顶电极; 位于衬底和栅极叠层上方的钝化氧化物层; 以及金属化以形成与有源区和栅叠层的接触。形成铁电存储晶体管的方法包括：制备基片，包括形成有源区和氧化物器件隔离区; 在栅极区域形成栅极占位符结构; 去除在栅极区域中形成栅极空隙的栅极占位符结构; 在结构上和栅极空隙中沉积高k绝缘体层以从高k杯沉积; 用铁电材料填充高k杯以形成铁电元件; 沉积高k上绝缘体层并去除多余的高k材料以在铁电元件上形成高k帽; 在顶部电极上沉积高k帽以形成栅电极和栅叠层; 在结构上沉积一层钝化氧化物; 将钝化氧化物从接触孔蚀刻到有源区和栅叠层; 并且对结构进行金属化以完成铁电存储晶体管。

69. 发明授权

US06649957B2 Thin film polycrystalline memory structure 失效
标题翻译：薄膜多晶记忆结构
公开(公告)号：US06649957B2
公开(公告)日：2003-11-18
申请号：US10345725
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei-Wei Zhuang
IPC分类号： H01L2976
CPC分类号： H01L28/56 , G11C13/0007 , G11C2213/31 , H01L21/28291 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
摘要翻译：描述了一种多晶体存储器结构，用于提高使用多晶存储材料的器件的可靠性和产量，所述多晶存储器材料包括多晶存储层绝缘材料至少部分地位于间隙内以至少部分地阻挡对间隙的入口。还描述了形成多晶存储器结构的方法。沉积和退火一层材料以形成在相邻微晶之间具有间隙的多晶记忆材料。绝缘材料沉积在多晶记忆材料上以至少部分地填充间隙，从而阻挡每个间隙的一部分。

70. 发明授权

US06586260B2 Single c-axis PGO thin film electrodes having good surface smoothness and uniformity and methods for making the same 失效
公开(公告)号：US06586260B2
公开(公告)日：2003-07-01
申请号：US09820078
申请日：2001-03-28
申请人： Fengyan Zhang , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/65 , C23C16/40 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75 , Y10T428/24917 , Y10T428/2495
摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

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