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61. 发明授权

US07478081B2 Selection of a set of optimal n-grams for indexing string data in a DBMS system under space constraints introduced by the system 有权
标题翻译：在系统引入的空间约束下，选择一组用于在DBMS系统中索引字符串数据的最佳n-gram
公开(公告)号：US07478081B2
公开(公告)日：2009-01-13
申请号：US10981895
申请日：2004-11-05
申请人： Vahit Hakan Hacigumus , Balakrishna Raghavendra Iyer , Sharad Mehrotra
发明人： Vahit Hakan Hacigumus , Balakrishna Raghavendra Iyer , Sharad Mehrotra
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30619 , G06F17/30625 , Y10S707/99932 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99942 , Y10S707/99943
摘要： The present invention provides a computer-readable medium and system for selecting a set of n-grams for indexing string data in a DBMS system. Aspects of the invention include providing a set of candidate n-grams, each n-gram comprising a sequence of characters; identifying sample queries having character strings containing the candidate n-grams; and based on the set of candidate n-grams, the sample queries, database records, and an n-gram space constraint, automatically selecting, given the space constraint, a minimal set of an n-grams from the set of candidate n-grams that minimizes the number of false hits for the set of sample queries had the sample queries been executed against the database records.
摘要翻译：本发明提供了一种用于在DBMS系统中选择用于索引字符串数据的一组n-gram的计算机可读介质和系统。本发明的方面包括提供一组候选n克，每个n-gram包括一系列字符; 识别具有包含候选n-gram的字符串的样本查询; 并且基于候选n-gram的集合，样本查询，数据库记录和n-gram空间约束，给定空间约束，从候选n-gram集合中自动选择n-gram的最小集合这可以最小化针对数据库记录执行样本查询的一组样本查询的假命中数。

62. 发明授权

US07418536B2 Processor having systolic array pipeline for processing data packets 有权
标题翻译：具有用于处理数据包的收缩阵列管线的处理器
公开(公告)号：US07418536B2
公开(公告)日：2008-08-26
申请号：US11326253
申请日：2006-01-04
申请人： Arthur Tung-Tak Leung , Anthony Li , William Lynch , Sharad Mehrotra
发明人： Arthur Tung-Tak Leung , Anthony Li , William Lynch , Sharad Mehrotra
IPC分类号： G06F13/36
CPC分类号： H04L45/00 , H04L45/54 , H04L45/60 , H04L49/3009
摘要： A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
摘要翻译：一种用于路由器的处理器，所述处理器具有用于处理数据分组的收缩阵列流水线，以确定路由器的哪个输出端口应该路由数据分组。在一个实施例中，收缩阵列管线包括多个可编程功能单元和按顺序排列的寄存器文件，用于在程序化控制下处理分组上下文（其包含分组的目的地地址）以执行操作，以确定目标端口路由器为数据包。收缩阵列的单级可以包含寄存器文件和一个或多个功能单元，例如加法器，移位器，逻辑单元等，用于在一个示例中执行非常长的指令字（vliw）操作。处理器还可以包括用于存储路由信息的片上转发表存储器，以及选择性地将收缩阵列的级与转发表存储器连接的交叉条。

63. 发明授权

US07382787B1 Packet routing and switching device 有权
标题翻译：分组路由和交换设备
公开(公告)号：US07382787B1
公开(公告)日：2008-06-03
申请号：US10177496
申请日：2002-06-20
申请人： Peter M. Barnes , Nikhil Jayaram , Anthony J. Li , William L. Lynch , Sharad Mehrotra
发明人： Peter M. Barnes , Nikhil Jayaram , Anthony J. Li , William L. Lynch , Sharad Mehrotra
IPC分类号： H04L12/28
CPC分类号： H04L12/66
摘要： A method for routing and switching data packets from one or more incoming links to one or more outgoing links of a router. The method comprises receiving a data packet from the incoming link, assigning at least one outgoing link to the data packet based on the destination address of the data packet, and after the assigning operation, storing the data packet in a switching memory based on the assigned outgoing link. The data packet extracted from the switching memory, and transmitted along the assigned outgoing link. The router may include a network processing unit having one or more systolic array pipelines for performing the assigning operation.
摘要翻译：一种用于将数据分组从一个或多个传入链路路由和切换到路由器的一个或多个输出链路的方法。该方法包括从输入链路接收数据分组，基于数据分组的目的地地址向数据分组指派至少一个输出链路，并且在分配操作之后，基于所分配的数据分组将数据分组存储在切换存储器中传出链接。从切换存储器提取的数据分组，并沿着分配的输出链路传输。路由器可以包括具有用于执行分配操作的一个或多个收缩阵列管线的网络处理单元。

64. 发明申请

US20080066044A1 Enhanced Routing Grid System And Method 审中-公开
标题翻译：增强路由网格系统和方法
公开(公告)号：US20080066044A1
公开(公告)日：2008-03-13
申请号：US11934554
申请日：2007-11-02
申请人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
发明人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.
摘要翻译：提供了路由系统和方法，其具有用于优化和评估网表连接的可能路由的各种策略。在一个实施例中，数据结构或矩阵提供加权的成本相关数据，以评估连接或分段将对感兴趣的属性（例如速度，可制造性或噪声容限）提出的影响。该成本信息可以与地形成本以及形状成本相关联，以提供用于连接的多维成本信息。使用比计算密集型迭代乘法过程要求低的加法过程，处理这种更高信息成本数据变得更有效。还公开了用于移动和调整路由网格以改进对可用空间的使用或减少路由中的运行时间的各种方法。在另一个实施例中，使用并行处理方案来同时处理多个处理器上的多个区域而不会产生冲突，例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。

65. 发明授权

US07069372B1 Processor having systolic array pipeline for processing data packets 失效
标题翻译：具有用于处理数据包的收缩阵列管线的处理器
公开(公告)号：US07069372B1
公开(公告)日：2006-06-27
申请号：US10177187
申请日：2002-06-20
申请人： Arthur Leung, Jr. , Anthony J. Li , William L. Lynch , Sharad Mehrotra
发明人： Arthur Leung, Jr. , Anthony J. Li , William L. Lynch , Sharad Mehrotra
IPC分类号： G06F1/00
CPC分类号： G06F9/3867 , G06F9/3802 , G06F15/8046 , H04L45/60 , H04L49/3009
摘要： A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
摘要翻译：一种用于路由器的处理器，所述处理器具有用于处理数据分组的收缩阵列流水线，以确定路由器的哪个输出端口应该路由数据分组。在一个实施例中，收缩阵列管线包括多个可编程功能单元和按顺序排列的寄存器文件，用于在程序化控制下处理分组上下文（其包含分组的目的地地址）以执行操作，以确定目标端口路由器为数据包。收缩阵列的单级可以包含寄存器文件和一个或多个功能单元，例如加法器，移位器，逻辑单元等，用于在一个示例中执行非常长的指令字（vliw）操作。处理器还可以包括用于存储路由信息的片上转发表存储器，以及选择性地将收缩阵列的级与转发表存储器连接的交叉条。

66. 发明申请

US20060117126A1 Processing unit for efficiently determining a packet's destination in a packet-switched network 有权
标题翻译：处理单元，用于在分组交换网络中有效地确定分组的目的地
公开(公告)号：US20060117126A1
公开(公告)日：2006-06-01
申请号：US11326253
申请日：2006-01-04
申请人： Arthur Leung , Anthony Li , William Lynch , Sharad Mehrotra
发明人： Arthur Leung , Anthony Li , William Lynch , Sharad Mehrotra
IPC分类号： G06F13/36
CPC分类号： H04L45/00 , H04L45/54 , H04L45/60 , H04L49/3009
摘要： A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
摘要翻译：一种用于路由器的处理器，所述处理器具有用于处理数据分组的收缩阵列流水线，以确定路由器的哪个输出端口应该路由数据分组。在一个实施例中，收缩阵列管线包括多个可编程功能单元和按顺序排列的寄存器文件，用于在程序化控制下处理分组上下文（其包含分组的目的地地址）以执行操作，以确定目标端口路由器为数据包。收缩阵列的单级可以包含寄存器文件和一个或多个功能单元，例如加法器，移位器，逻辑单元等，用于在一个示例中执行非常长的指令字（vliw）操作。处理器还可以包括用于存储路由信息的片上转发表存储器，以及选择性地将收缩阵列的级与转发表存储器连接的交叉条。

67. 发明申请

US20060064384A1 Apparatus and method for privacy protection of data collection in pervasive environments 有权
标题翻译：用于普及环境中数据收集的隐私保护的装置和方法
公开(公告)号：US20060064384A1
公开(公告)日：2006-03-23
申请号：US11227721
申请日：2005-09-14
申请人： Sharad Mehrotra , Mohanned Alhazzazi , Mahesh Datt , Nalini Venkatasubramanian , Jehan Wickramasuriya
发明人： Sharad Mehrotra , Mohanned Alhazzazi , Mahesh Datt , Nalini Venkatasubramanian , Jehan Wickramasuriya
IPC分类号： G06Q99/00 , H04N7/18 , G05B19/00
CPC分类号： H04N7/181 , G01S3/7864 , G07C9/00111 , G08B13/19608 , G08B13/19645 , G08B13/19673 , G08B13/19686 , G08B13/19695
摘要： A security system which is nonintrusive of personal privacy of a person in a space comprises at least a first localization sensor subsystem, if any, in the possession of the person; a video surveillance subsystem arranged and configured to collect visual data related to the person in the space; and a computer subsystem coupled to the localization sensor subsystem and video surveillance subsystem to associate a predetermined privacy level with the localization sensor subsystem, and to provide an access control privilege with the localization sensor subsystem, the computer subsystem determining how to present, store and/or retrieve the visual data while meeting predetermined the privacy level associated with the person.
摘要翻译：非侵入个人空间的个人隐私的安全系统至少包括由该人管有的第一定位传感器子系统（如果有的话）; 视频监控子系统被布置和配置为收集与该空间中的人有关的视觉数据; 以及耦合到所述定位传感器子系统和视频监视子系统以将预定隐私级别与所述定位传感器子系统相关联的计算机子系统，并且与所述定位传感器子系统提供访问控制特权，所述计算机子系统确定如何呈现，存储和/ 或者在满足预定的与个人相关联的隐私级别的同时检索视觉数据。

68. 发明授权

US06735754B2 Method and apparatus to facilitate global routing for an integrated circuit layout 有权
标题翻译：促进集成电路布局的全局路由的方法和装置
公开(公告)号：US06735754B2
公开(公告)日：2004-05-11
申请号：US10165136
申请日：2002-06-06
申请人： Sharad Mehrotra , Parsotam T. Patel
发明人： Sharad Mehrotra , Parsotam T. Patel
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A system that facilitates generating a global routing for a layout of an integrated circuit operates by receiving a netlist to be routed. The system partitions this netlist into global signals, datapath signals, and control signals. Next, the system creates a tiling grid of the integrated circuit and routes connection nets between tiles within this grid. The system then selects an area within the integrated circuit larger than a tile in the first grid. The system creates a second grid of tiles smaller than the tiles of the first grid within this selected area. During this process, connection nets are routed between tiles on the second grid while routings within the first grid are maintained. The system merges connection nets within the first grid with connection nets within the second grid to form the global routing.
摘要翻译：有助于生成用于集成电路的布局的全局路由的系统通过接收要路由的网表进行操作。系统将该网表分为全局信号，数据路径信号和控制信号。接下来，系统创建集成电路的平铺网格，并在该网格内的网格之间路由连接网。然后，系统选择集成电路内的区域大于第一格栅中的瓦片。该系统创建小于该选定区域内第一个网格的瓦片的第二格网格。在此过程中，连接网络在第二网格上的瓦片之间路由，同时维护第一网格内的路由。系统将第一个网格内的连接网络与第二个网格内的连接网络合并，形成全局路由。

69. 发明授权

US06430654B1 Apparatus and method for distributed non-blocking multi-level cache 失效
标题翻译：分布式非阻塞多级缓存的装置和方法
公开(公告)号：US06430654B1
公开(公告)日：2002-08-06
申请号：US09010072
申请日：1998-01-21
申请人： Sharad Mehrotra , Ricky C. Hetherington
发明人： Sharad Mehrotra , Ricky C. Hetherington
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F12/0897
摘要： A multi-level cache and method for operation therefore includes a first non-blocking cache receiving access requests from a device in a processor, and a first miss queue storing entries corresponding to access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided for receiving access requests from the first miss queue, and a second miss queue is provided for storing entries corresponding to access requests not serviced by the second non-blocking cache. Other queueing structures such as a victim queue and a write queue are provided depending on the particular structure of the cache level within the multilevel cache hierarchy.
摘要翻译：因此，用于操作的多级缓存和方法包括接收来自处理器中的设备的访问请求的第一非阻塞缓存和存储与未被第一非阻塞高速缓存服务的访问请求相对应的条目的第一未命中队列。第二非阻塞缓存被提供用于接收来自第一未命中队列的访问请求，并且提供第二未命中队列用于存储对应于未由第二非阻塞缓存服务的访问请求的条目。取决于多级高速缓存层次结构中的高速缓存级别的特定结构，提供其他排队结构，例如受害者队列和写队列。

70. 发明授权

US6061508A Modeling and processing of on-chip interconnect capacitance 失效
标题翻译：片上互连电容的建模和处理
公开(公告)号：US6061508A
公开(公告)日：2000-05-09
申请号：US888060
申请日：1997-07-03
申请人： Sharad Mehrotra , Jagannathan Narasimhan , Albert Emil Ruehli
发明人： Sharad Mehrotra , Jagannathan Narasimhan , Albert Emil Ruehli
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.
摘要翻译：提出了一种用于任意几何形状的芯片环境中的电容分析的装置和方法。它使用结合二维确定的过程，其中选择长度以适合解决方案。此外，所需的精度可以被限制在误差范围内。该技术也适用于三维电容的分析，重要的也可用于二维和三维电容确定的混合。在一个实施例中，该过程将空间划分成一组子空间。使用平行板电容公式确定子空间的电容值。

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