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61. 发明申请

US20070201592A1 Multi-channel fractional clock data transfer 有权
$Multi-channel fractional clock data transfer$
标题翻译：多通道小数时钟数据传输
公开(公告)号：US20070201592A1
公开(公告)日：2007-08-30
申请号：US11363650
申请日：2006-02-28
申请人： Subramaniam Maiyuran , Christopher Gianos
发明人： Subramaniam Maiyuran , Christopher Gianos
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , G06F5/065 , H04L7/005
摘要： Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a signal corresponding to a read pointer of a buffer is generated in response to a plurality of signals that correspond to write pointers of the buffer.
摘要翻译：描述了在一个或多个时钟域之间传送数据的方法和装置。在一个实施例中，响应于对应于缓冲器的写指针的多个信号而产生对应于缓冲器的读指针的信号。

62. 发明授权

US06898674B2 Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers 失效
标题翻译：用于在处理器和存储器控制器之间同步信息预取的装置，方法和系统
公开(公告)号：US06898674B2
公开(公告)日：2005-05-24
申请号：US10170171
申请日：2002-06-11
申请人： Subramaniam Maiyuran , David McDonnell
发明人： Subramaniam Maiyuran , David McDonnell
IPC分类号： G06F12/02 , G06F12/08 , G06F13/16 , G06F12/00
CPC分类号： G06F12/0215 , G06F12/0862 , G06F13/161 , G06F2212/6026 , G06F2212/6028
摘要： According to one embodiment of the invention, a prefetcher in a memory controller is described which includes logic to receive memory request hints from a CPU. The memory request hints are used by the prefetcher in the memory controller to prefetch information from one or more memory devices coupled to the memory controller via a memory bus. The prefetcher in the memory controller further includes logic to determine the types of memory request hints provided by the CPU, the types of memory request hints are used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request. The prefetcher in the memory controller also includes logic to generate prefetch requests to prefetch information from the one or more memory devices, based on the types of memory request hints provided by the CPU and bandwidth availability of the memory bus.
摘要翻译：根据本发明的一个实施例，描述了存储器控制器中的预取器，其包括从CPU接收存储器请求提示的逻辑。存储器请求提示被存储器控制器中的预取器用于从经由存储器总线耦合到存储器控制器的一个或多个存储器件预取信息。存储器控制器中的预取器还包括确定由CPU提供的存储器请求提示的类型的逻辑，存储器请求提示的类型用于指示由CPU提供的提示是用于指令存储器读请求还是数据存储器读请求。存储器控制器中的预取器还包括基于由CPU提供的存储器请求提示的类型和存储器总线的带宽可用性来生成预取请求以从一个或多个存储器设备预取信息的逻辑。

63. 发明授权

US06175253B1 Fast bi-directional tristateable line driver 失效
标题翻译：快速双向三向线驱动
公开(公告)号：US06175253B1
公开(公告)日：2001-01-16
申请号：US09052883
申请日：1998-03-31
申请人： Subramaniam Maiyuran , Sanjay Dabral , Thu M. Do , Scott E. Siers , Mehrdad Mohebbi
发明人： Subramaniam Maiyuran , Sanjay Dabral , Thu M. Do , Scott E. Siers , Mehrdad Mohebbi
IPC分类号： H03K1902
CPC分类号： H03K19/018592 , H03K19/09429
摘要： A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.
摘要翻译：驱动器，其在驱动阶段期间根据数据信号驱动具有上拉和下拉晶体管的总线，并且在使用所述上拉和下拉晶体管的前提阶段期间将所述总线充电或放电到中间电压电平，所述驱动器包括缓冲器和在驱动阶段结束时锁存总线电压; 当前一个驱动阶段的总线电压为低电平时，响应锁存器的开关状态，在预处理阶段开始时接通上拉晶体管，以便将总线电压充电到小于电源电压的第一电压，在前一个驱动阶段的总线电压为高电平时，在预处理阶段开始时，接通一个下拉晶体管，以便将总线电压放电到地面以上的第二个电压。

64. 发明申请

US20190244418A1 CONDITIONAL SHADER FOR GRAPHICS 审中-公开
公开(公告)号：US20190244418A1
公开(公告)日：2019-08-08
申请号：US16269270
申请日：2019-02-06
申请人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
IPC分类号： G06T15/80 , G06F9/50 , G06T1/20 , G06T5/20
CPC分类号： G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

65. 发明申请

US20180285374A1 ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE 审中-公开
公开(公告)号：US20180285374A1
公开(公告)日：2018-10-04
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F17/30 , G06F9/38 , G06F9/30
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

66. 发明申请

US20180285191A1 REFERENCE VOLTAGE CONTROL BASED ON ERROR DETECTION 审中-公开
公开(公告)号：US20180285191A1
公开(公告)日：2018-10-04
申请号：US15477050
申请日：2017-04-01
申请人： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
发明人： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
IPC分类号： G06F11/07
摘要： Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

67. 发明申请

US20180285158A1 HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS 审中-公开
公开(公告)号：US20180285158A1
公开(公告)日：2018-10-04
申请号：US15477026
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
发明人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
IPC分类号： G06F9/50 , G06T1/60 , G06T1/20 , G06T15/00 , G06F9/48 , G06F1/32
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

68. 发明授权

US09336008B2 Shared function multi-ported ROM apparatus and method 有权
标题翻译：共享功能多端口ROM设备和方法
公开(公告)号：US09336008B2
公开(公告)日：2016-05-10
申请号：US13338887
申请日：2011-12-28
申请人： Satish K. Damaraju , Subramaniam Maiyuran
发明人： Satish K. Damaraju , Subramaniam Maiyuran
IPC分类号： G06F9/30 , G06F9/38 , G06F7/544
CPC分类号： G06F9/3877 , G06F7/544 , G06F9/3001 , G06F9/30036
摘要： Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.
摘要翻译：可以公开可以在处理核心的多个端口中共享ROM下拉逻辑电路的各种实施例。处理核心可以包括具有存储数学函数的只读存储器（ROM）下拉逻辑阵列的执行单元（EU）。 ROM下拉逻辑电路可以实现单指令，多数据（SIMD）操作。 ROM下拉逻辑电路可以在多端口功能共享装置中与多个端口中的每一个可操作地耦合。共享ROM下拉逻辑电路减少了重复逻辑的需要，并且可以节省芯片面积以及节省功率。

69. 发明授权

US09183014B2 Enabling virtual calls in a SIMD environment 有权
标题翻译：在SIMD环境中启用虚拟呼叫
公开(公告)号：US09183014B2
公开(公告)日：2015-11-10
申请号：US13028574
申请日：2011-02-16
申请人： Wei-Yu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
发明人： Wei-Yu Chen , Guei-Yuan Lueh , Subramaniam Maiyuran
IPC分类号： G06F15/80 , G06F9/455 , G06F9/30 , G06F9/44
CPC分类号： G06F9/547 , G06F9/30061 , G06F9/449 , G06F9/455 , G06F15/8007
摘要： Systems and methods of enabling virtual calls in a single instruction multiple data (SIMD) environment may involve detecting a virtual call of a function and using a single dispatch of the function to invoke the virtual call for two or more channels of the virtual call. In one example, it is determined that the two or more channels share a common target address and a single dispatch of the function is conducted with respect to the common target address. The process may be iterated for additional channels of the virtual call that share a common target address.
摘要翻译：在单个指令多数据（SIMD）环境中启用虚拟呼叫的系统和方法可以涉及检测功能的虚拟呼叫，并且使用该功能的单个调度来调用虚拟呼叫的两个或多个信道的虚拟呼叫。在一个示例中，确定两个或更多个信道共享公共目标地址，并且相对于公共目标地址进行该功能的单个调度。可以对共享共同目标地址的虚拟呼叫的附加信道重复该过程。

70. 发明申请

US20150046736A1 Uncore Thermal Management 有权
标题翻译： Uncore热管理
公开(公告)号：US20150046736A1
公开(公告)日：2015-02-12
申请号：US14195737
申请日：2014-03-03
申请人： Deep Buch , Vivek Garg , Subramaniam Maiyuran
发明人： Deep Buch , Vivek Garg , Subramaniam Maiyuran
IPC分类号： G06F1/20 , G06F1/32
CPC分类号： G06F1/206 , G06F1/3287
摘要： A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
摘要翻译：描述了一种方法，其涉及通过一个无孔部来控制交通等级，以提供对该无孔的热管理。所述方法包括确定第一非核状态中的非空气温度是否高于第一阈值，并且如果所述非空温度高于所述第一阈值，则将所述第一非空状态改变为第二非空状态。

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