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61. 发明授权

US3999080A Transistor coupled logic circuit 失效
标题翻译：晶体管耦合逻辑电路
公开(公告)号：US3999080A
公开(公告)日：1976-12-21
申请号：US535405
申请日：1974-12-23
申请人： Scott Weathersby, Jr. , Earl C. Wilson , Benjamin J. Sloan , Robert C. Martin
发明人： Scott Weathersby, Jr. , Earl C. Wilson , Benjamin J. Sloan , Robert C. Martin
IPC分类号： H01L27/07 , H01L27/082 , H03K19/013 , H03K19/088 , H03K19/08 , H03K19/22 , H03K19/36
CPC分类号： H03K19/088 , H01L27/0755 , H01L27/0825 , H01L27/0826 , H03K19/013
摘要： A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.
摘要翻译：采用单发射极PNP输入晶体管而不是多发射极输入级的TTL逻辑电路，以减少输入驱动器件的负载。该电路具有以1.6伏的电路阈值为中心的1.6伏特的逻辑摆幅，逻辑0和逻辑1电平内部钳位pn二极管结，以防止晶体管饱和，并提高晶体管的切换速度超过通常使用肖特基二极管钳位技术获得的晶体管开关速度。电路输出包含达林顿级，并提供逻辑1驱动能力，允许电路驱动具有低特性阻抗（通常为50欧姆）的终止信号线，同时在25℃保持高于2.0伏特的逻辑1电平。使用离子注入限定隔离，发射极和基极区域以及pn二极管接头的技术允许较小的器件几何形状和能够进行高速切换的高FT晶体管。

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