专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08955370B1 Detection of gas leakage 有权
标题翻译：气体泄漏检测
公开(公告)号：US08955370B1
公开(公告)日：2015-02-17
申请号：US13473063
申请日：2012-05-16
申请人： Steven M. Thornberg , Jason Brown
发明人： Steven M. Thornberg , Jason Brown
IPC分类号： G01M3/32
CPC分类号： G01M3/34 , G01M3/3263
摘要： A method of detecting leaks and measuring volumes as well as a device, the Power-free Pump Module (PPM), provides a self-contained leak test and volume measurement apparatus that requires no external sources of electrical power during leak testing or volume measurement. The PPM is a portable, pneumatically-controlled instrument capable of generating a vacuum, calibrating volumes, and performing quantitative leak tests on a closed test system or device, all without the use of alternating current (AC) power. Capabilities include the ability is to provide a modest vacuum (less than 10 Torr) using a venturi pump, perform a pressure rise leak test, measure the gas's absolute pressure, and perform volume measurements. All operations are performed through a simple rotary control valve which controls pneumatically-operated manifold valves.
摘要翻译：检测泄漏和测量体积的方法以及无功耗泵模块（PPM）的设备提供了独立的泄漏测试和体积测量设备，在泄漏测试或体积测量期间不需要外部电源。 PPM是一种便携式气动控制仪器，能够在封闭的测试系统或设备上产生真空，校准体积和进行定量泄漏测试，所有这些都不使用交流（AC）电源。能力包括使用文丘里泵提供适度真空（小于10乇）的能力，执行压力上升泄漏测试，测量气体的绝对压力并进行体积测量。所有操作都通过简单的旋转控制阀执行，该控制阀控制气动操作的歧管阀。

62. 发明申请

US20140377251A1 FORMULATION FOR ANTI-ALPHA4BETA7 ANTIBODY 有权
标题翻译：抗ALPHA4BETA7抗体的配方
公开(公告)号：US20140377251A1
公开(公告)日：2014-12-25
申请号：US14114832
申请日：2012-05-02
申请人： Willow Diluzio , Nobel T. Truong , Csanad M. Varga , Vaithianathan Palaniappan , Jason Brown , Irving H. Fox , Catherine Scholz
发明人： Willow Diluzio , Nobel T. Truong , Csanad M. Varga , Vaithianathan Palaniappan , Jason Brown , Irving H. Fox , Catherine Scholz
IPC分类号： A61K47/26 , A61K47/18 , A61K39/395
CPC分类号： A61K47/26 , A61K9/0019 , A61K9/19 , A61K39/39591 , A61K47/183 , A61K2039/505 , A61K2039/54 , A61K2039/545 , C07K16/2839 , C07K2317/14 , C07K2317/24 , C07K2317/565 , C07K2317/92 , C07K2317/94
摘要： Antibody formulations are described comprising a mixture of a non-reducing sugar, an anti-α4β7 antibody and at least one amino acid. The disclosed formulations have improved stability, reduced aggregate formation, and may retard degradation of the anti-α4β7 antibody therein or exhibit any combinations thereof. The present invention further provides a safe dosing regimen of these antibody formulations that is easy to follow, and which results in a therapeutically effective amount of the anti-α4β7 anti body in vivo.
摘要翻译：描述了包含非还原糖，抗α4和bgr7抗体和至少一种氨基酸的混合物的抗体制剂。所公开的制剂具有改善的稳定性，减少的聚集体形成，并且可以阻止其中的抗α4和bgr7抗体的降解或显示其任何组合。本发明还提供了易于遵循的这些抗体制剂的安全给药方案，并且其在体内导致治疗有效量的抗α4和抗体。

63. 发明申请

US20140341885A1 FORMULATION FOR ANTI-ALPHA4BETA7 ANTIBODY 审中-公开
标题翻译：抗ALPHA4BETA7抗体的配方
公开(公告)号：US20140341885A1
公开(公告)日：2014-11-20
申请号：US14114835
申请日：2012-05-02
申请人： Willow Diluzio , Phuong M. Nguyen , Csanad M. Varga , Vaithianathan Palaniappan , Jason Brown , Irving H. Fox , Catherine Scholz , Erica Helen Jenkins , Maria Rosario
发明人： Willow Diluzio , Phuong M. Nguyen , Csanad M. Varga , Vaithianathan Palaniappan , Jason Brown , Irving H. Fox , Catherine Scholz , Erica Helen Jenkins , Maria Rosario
IPC分类号： C07K16/28
CPC分类号： C07K16/2839 , A61K9/0019 , A61K39/39591 , A61K47/12 , A61K47/14 , A61K47/183 , A61K47/26 , A61K2039/505 , A61K2039/54 , A61K2039/545 , C07K2317/24
摘要： Antibody formulations are described comprising a mixture of an anti-α4β7 antibody, an antioxidant or chelator, and at least one free amino acid. The disclosed formulations may have improved stability, reduced aggregate formation, or both. The present invention further provides a safe dosing regimen of these antibody formulations that is easy to follow, and which results in a therapeutically effective amount of the anti-α4β7 antibody in vivo.
摘要翻译：描述了包含抗α4和bgr7抗体，抗氧化剂或螯合剂和至少一种游离氨基酸的混合物的抗体制剂。所公开的制剂可以具有改善的稳定性，减少的聚集体形成或两者。本发明进一步提供了易于遵循的这些抗体制剂的安全给药方案，并且其在体内导致治疗有效量的抗α4和bgr7抗体。

64. 发明授权

US08023343B2 Systems and methods for issuing address and data signals to a memory array 有权
标题翻译：将地址和数据信号发送到存储器阵列的系统和方法
公开(公告)号：US08023343B2
公开(公告)日：2011-09-20
申请号：US12771578
申请日：2010-04-30
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.
摘要翻译：本发明的实施例包括使用系统时钟和写时钟将地址和数据信号发送到存储器阵列的电路。可以使用锁定环来补偿系统时钟相对于写入时钟所经历的附加延迟并确保时钟信号的同步。可以使用写锁存器使能块来产生用于发出的写锁存器使能信号以及相应的地址信号。写锁存器使能信号可以被定时使得其到达适当的时间以发出对应于发出的地址的数据。

65. 外观设计

USD641121S1 Receptacle 有权
公开(公告)号：USD641121S1
公开(公告)日：2011-07-05
申请号：US29369130
申请日：2010-09-02
申请人： Kurt Rampton , Edgar Montague , William M. Riley , Sean D. Anderson , Jason Brown , Brian Fultz , Claude Q. Brack
设计人： Kurt Rampton , Edgar Montague , William M. Riley , Sean D. Anderson , Jason Brown , Brian Fultz , Claude Q. Brack

66. 发明授权

US07953445B2 Multiple subscription subscriber identity module (SIM) card 有权
标题翻译：多个订阅用户识别模块（SIM）卡
公开(公告)号：US07953445B2
公开(公告)日：2011-05-31
申请号：US12581594
申请日：2009-10-19
申请人： Jason Brown
发明人： Jason Brown
IPC分类号： H04B1/40
CPC分类号： H04W8/245 , H04L63/0853 , H04W88/02
摘要： Embodiments of the invention include a multiple subscription subscriber identity module (SIM) card. The SIM card includes a plurality of sets of subscription parameters from which to select and activate a single set of parameters. The sets of subscription parameters each contain various information, e.g., information such as an Integrated Circuit Card Identifier (ICCID) and an International Mobile Subscriber Identity (IMSI), and are based on various criteria, e.g., different service regions of use for the electronic device on which the SIM card is installed. A set of subscription parameters is selected for a particular region of use either manually or automatically. The SIM card, which can include a software interface that provides a list of available sets of subscription parameters, is activated by updating the selected set of subscription parameters. Alternatively, a default set of subscription parameters is selected unless a different set of subscription parameters is selected manually from among the plurality of sets of subscription parameters. According to alternative embodiments of the invention, the selected set of subscription parameters can be deactivated and a different set of subscription parameters can be selected and updated to in the SIM card.
摘要翻译：本发明的实施例包括多个订阅订户身份模块（SIM）卡。 SIM卡包括多组订阅参数，从中选择和激活一组参数。订阅参数集合各自包含各种信息，例如诸如集成电路卡标识符（ICCID）和国际移动用户标识（IMSI）的信息，并且基于各种标准，例如用于电子的不同服务区域设备上安装了SIM卡。手动或自动为特定使用区域选择一组订阅参数。可以通过更新所选择的订阅参数集来激活SIM卡，该SIM卡可以包括提供可用订阅参数集合的列表的软件接口。或者，选择默认的订阅参数集合，除非从多个订阅参数集中手动选择不同的订阅参数集合。根据本发明的替代实施例，可以取消所选择的订阅参数集合，并且可以在SIM卡中选择并更新不同的订阅参数集合。

67. 发明申请

US20100254198A1 WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME 有权
标题翻译：写命令和写数据时序电路及其相同的方法
公开(公告)号：US20100254198A1
公开(公告)日：2010-10-07
申请号：US12416761
申请日：2009-04-01
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： G11C7/00 , G11C8/18 , G11C8/00
CPC分类号： G11C7/10 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2272
摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. The FF circuit latches the internal write command in response to an internal write command FF signal based on a write clock signal and generates an internal write enable signal in response to latching the internal write command. The write data register captures write data in response to the write clock signal and releases the captured write data in response to a delayed internal write enable signal.
摘要翻译：用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。定时电路还包括写平均触发器（FF）电路和写数据寄存器。 FF电路基于写入时钟信号来响应于内部写入命令FF信号而锁存内部写入命令，并且响应于锁存内部写入命令而产生内部写入使能信号。写数据寄存器响应于写时钟信号捕获写数据，并响应于延迟的内部写允许信号释放捕获的写数据。

68. 发明授权

US07729182B2 Systems and methods for issuing address and data signals to a memory array 有权
标题翻译：将地址和数据信号发送到存储器阵列的系统和方法
公开(公告)号：US07729182B2
公开(公告)日：2010-06-01
申请号：US12203533
申请日：2008-09-03
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.
摘要翻译：本发明的实施例包括使用系统时钟和写时钟将地址和数据信号发送到存储器阵列的电路。可以使用锁定环来补偿系统时钟相对于写入时钟所经历的附加延迟并确保时钟信号的同步。可以使用写锁存器使能块来产生用于发出的写锁存器使能信号以及相应的地址信号。写锁存器使能信号可以被定时使得其到达适当的时间以发出对应于发出的地址的数据。

69. 发明申请

US20100026344A1 METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER 有权
标题翻译：高电压缓冲器的方法，器件和系统
公开(公告)号：US20100026344A1
公开(公告)日：2010-02-04
申请号：US12577506
申请日：2009-10-12
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721
摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices.
摘要翻译：公开了方法，装置和系统，包括用于具有被配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。一个这样的缓冲器可以包括多个预驱动器，其中多个预驱动器中的每个预驱动器可操作地耦合到多个晶体管的晶体管。缓冲器还可以包括一个或多个钳位装置，其中多个晶体管中的至少一个晶体管具有耦合到一个或多个钳位装置的至少一个夹持装置的栅极。

70. 发明授权

US07605611B2 Methods, devices, and systems for a high voltage tolerant buffer 有权
标题翻译：用于高电压容限缓冲器的方法，设备和系统
公开(公告)号：US07605611B2
公开(公告)日：2009-10-20
申请号：US11877868
申请日：2007-10-24
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721
摘要： Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor, a primary pull-down pre-driver operably coupled to a primary pull-down transistor, and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. Each of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver are configured to provide a voltage to a gate of a transistor operably coupled thereto at a voltage level so as to sustain gate dielectric integrity of the transistor.
摘要翻译：公开了方法，装置和系统，包括用于具有被配置为向薄栅介质晶体管提供电压的预驱动器电路的缓冲器。一个这样的缓冲器可以包括可操作地耦合到初级上拉晶体管的初级上拉预驱动器，可操作地耦合到次级上拉晶体管的次级上拉预驱动器，可操作地连接到次级上拉晶体管的主下拉预驱动器耦合到主下拉晶体管，以及可操作地耦合到次级下拉晶体管的次级下拉预驱动器。初级上拉预驱动器，次级上拉预驱动器，初级下拉预驱动器和次级下拉预驱动器中的每一个被配置为可操作地向晶体管的栅极提供电压以电压电平耦合到其，以维持晶体管的栅极电介质完整性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式