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61. 发明授权

US07881332B2 Configurable ports for a host ethernet adapter 失效
标题翻译：主机以太网适配器的可配置端口
公开(公告)号：US07881332B2
公开(公告)日：2011-02-01
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

62. 发明授权

US07873027B2 Database management system and method of using it to transmit packets 有权
标题翻译：数据库管理系统及其使用方法传输数据包
公开(公告)号：US07873027B2
公开(公告)日：2011-01-18
申请号：US11776487
申请日：2007-07-11
申请人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L45/54 , H04L12/56
摘要： A forwarding table, in a network device such as a router, used to forward packets in a communications network includes indicia whose state determine whether information contained in the forwarding table or information contained in the header portion of a packet is to be used to forward the packet to the next hop (i.e. next point in the route).
摘要翻译：用于在通信网络中转发分组的诸如路由器的网络设备中的转发表包括其状态确定包含在转发表中的信息或包含在分组的报头部分中的信息将被用于转发分组到下一跳（即路由中的下一个点）。

63. 发明授权

US07529224B2 Scheduler, network processor, and methods for weighted best effort scheduling 失效
标题翻译：调度器，网络处理器和加权最佳努力调度的方法
公开(公告)号：US07529224B2
公开(公告)日：2009-05-05
申请号：US11108485
申请日：2005-04-18
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L45/00 , H04L45/60 , H04L47/50 , H04L47/527
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，三入口日历结构提供加权最佳努力调度。多个不同的流中的每一个具有相关的进度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

64. 发明申请

US20090083611A1 APPARATUS FOR BLIND CHECKSUM AND CORRECTION FOR NETWORK TRANSMISSIONS 有权
标题翻译：用于网络传输的盲点检测和校正装置
公开(公告)号：US20090083611A1
公开(公告)日：2009-03-26
申请号：US12200985
申请日：2008-08-29
申请人： Claude BASSO , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude BASSO , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： G06F11/10
CPC分类号： H04L69/16 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L69/161
摘要： Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
摘要翻译：用于在网络传输中提供校验和的装置。在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。在分组发送之前，协议校验和被插入到分组中。

65. 发明申请

US20080317027A1 SYSTEM FOR REDUCING LATENCY IN A HOST ETHERNET ADAPTER (HEA) 审中-公开
标题翻译：用于减少主机以太网适配器（HEA）中的延迟的系统
公开(公告)号：US20080317027A1
公开(公告)日：2008-12-25
申请号：US12200970
申请日：2008-08-29
申请人： Claude BASSO , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude BASSO , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A system for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
摘要翻译：用于减少主机以太网适配器（HEA）中的延迟的系统包括以下内容。首先，HEA在HEA中接收到具有互联网协议（IP）头部和数据的分组。 HEA从IP头解析连接标识符，并访问HEA中的负缓存，以确定连接标识符是否不在HEA外部的存储器中。如果连接标识符不在存储器中，则HEA对数据包应用默认处理，从而通过减少对存储器的访问来减少延迟。

66. 发明申请

US20080298244A1 APPARATUS AND METHOD FOR CACHING LOOKUPS BASED UPON TCP TRAFFIC FLOW CHARACTERISTICS 失效
标题翻译：基于TCP流量特性的查询语言的设备和方法
公开(公告)号：US20080298244A1
公开(公告)日：2008-12-04
申请号：US12188333
申请日：2008-08-08
申请人： Everett A. Corl, JR. , Gordon T. Davis , Clark D. Jeffries , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Everett A. Corl, JR. , Gordon T. Davis , Clark D. Jeffries , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L69/22
摘要： The classification system of a network device includes a cache in which a mapping between predefined characteristics of TCP/IP packets and associated actions are stored in response to the first “Frequent Flyer” packet in of a session. Selected characteristics from subsequent received packets of that session are correlated with the predefined characteristics and the stored actions are applied to the received packets if the selected characteristics and the predefined characteristics match, thus reducing the processing required for subsequent packets. The packets selected for caching may be data packets. For mismatched characteristics, the full packet search of the classification system is used to determine the action to apply to the received packet.
摘要翻译：网络设备的分类系统包括缓存，其中响应于会话中的第一“频繁传单”分组而存储TCP / IP分组的预定义特性与相关动作之间的映射。如果所选择的特征和预定义的特征匹配，则从该会话的后续接收到的分组中选出的特征与预定义的特征相关联，并且将存储的动作应用于所接收的分组，从而减少后续分组所需的处理。选择用于缓存的数据包可能是数据包。对于不匹配的特征，分类系统的全分组搜索用于确定应用于接收到的分组的动作。

67. 发明申请

US20080181245A1 System and Method for Multicore Communication Processing 有权
标题翻译：多核通信处理系统与方法
公开(公告)号：US20080181245A1
公开(公告)日：2008-07-31
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L47/50
摘要： A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了一种用于数据处理设备之间的通信的多核处理的系统和方法。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

68. 发明申请

US20080046797A1 APPARATUS, METHOD AND PROGRAM PRODUCT TO GENERATE AND USE CRC IN COMMUNICATIONS NETWORK 失效
标题翻译：在通信网络中生成和使用CRC的装置，方法和程序产品
公开(公告)号：US20080046797A1
公开(公告)日：2008-02-21
申请号：US11875995
申请日：2007-10-22
申请人： James Allen , Jean Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： James Allen , Jean Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H03M13/09
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.
摘要翻译：用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC生成器使用2.sup.16位来生成第二个CRC表。通过将CID字段，LI字段和UUI字段中的位与两个表相关来生成特定CPS头的CRC。

69. 发明授权

US07283529B2 Method and system for supporting a dedicated label switched path for a virtual private network over a label switched communication network 有权
标题翻译：用于在标签交换通信网络上支持用于虚拟专用网络的专用标签交换路径的方法和系统
公开(公告)号：US07283529B2
公开(公告)日：2007-10-16
申请号：US10383973
申请日：2003-03-07
申请人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： H04L12/28 , H04L12/56 , G06F15/173
CPC分类号： H04L45/54 , H04L12/4641 , H04L45/50
摘要： A system and method for transmitting data from a first site to a second site over a shared Multi-Protocol Label Switched (MPLS) network comprising a plurality of routers, including an ingress router in communication with the first site and an egress router in communication with the second site, includes configuring a plurality of label switching paths between the ingress router and the egress router over a plurality of label switching devices. The method further includes performing a first lookup on one of at least one virtual routing and forwarding (VRF) table stored in the ingress router, whereby the first lookup identifies one routing table from a plurality of routing tables stored in the ingress router, each routing table being associated with one of the plurality of label switched paths, and performing a second lookup on the one routing table, wherein the routing table defines the associated label switched path between the ingress router and the egress router for a virtual private network (VPN) between the first site and the second site.
摘要翻译：一种用于通过共享的多协议标签交换（MPLS）网络从第一站点传送数据到第二站点的系统和方法，包括多个路由器，包括与第一站点通信的入口路由器和与第一站点通信的出口路由器第二站点包括通过多个标签交换设备在入口路由器和出口路由器之间配置多个标签交换路径。该方法还包括对存储在入口路由器中的至少一个虚拟路由和转发（VRF）表中的一个执行第一查找，由此第一查找从存储在入口路由器中的多个路由表中识别一个路由表，每个路由表与多个标签交换路径中的一个相关联，并且在一个路由表上执行第二查找，其中该路由表定义入口路由器与用于虚拟专用网（VPN）的出口路由器之间的关联标签交换路径，在第一个站点和第二个站点之间。

70. 发明申请

US20060245443A1 Systems and methods for rate-limited weighted best effort scheduling 失效
公开(公告)号：US20060245443A1
公开(公告)日：2006-11-02
申请号：US11119329
申请日：2005-04-29
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/28 , G01R31/08
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.

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