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61. 发明授权

US5894582A Method of controlling parallel processing at an instruction level and processor for realizing the method 失效
标题翻译：在指令级别控制并行处理的方法和用于实现该方法的处理器
公开(公告)号：US5894582A
公开(公告)日：1999-04-13
申请号：US596628
申请日：1996-02-05
申请人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
发明人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3853
摘要： Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction buffer, an instruction register unit for storing and issuing the sent instructions to a plurality of execution units in the order of instruction, and a judgement part for judging whether it is possible to execute a set of unissued instructions to be next issued, in parallel, as stored in the instruction buffer and/or the instruction register unit and for controlling parallel processing of the set of instructions, based on the result of a judgement on the possibility of parallel processing.
摘要翻译：用于实现指令级并行处理的装置包括：指令缓冲器，用于存储从指令缓冲器发送指令之前从存储器取出的指令;指令寄存器单元，用于以指令顺序存储并发布发送指令给多个执行单元; 以及用于判断是否可以并行地执行存储在指令缓冲器和/或指令寄存器单元中并用于控制该组指令的并行处理的一组未发布指令的判断部分，基于对并行处理可能性的判断结果。

62. 发明授权

US5713012A Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US5713012A
公开(公告)日：1998-01-27
申请号：US717143
申请日：1996-09-20
申请人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
发明人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3885
摘要： A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through the N-th processing units. On the other hand, wherein a branch instruction (k-th instruction) is included in the N sequential instructions, the function logic operates such that the first through the k-th instructions are parallelly executed by the (N-p+1)-th through the N-th processing units.
摘要翻译：微处理器具有N个处理单元，用于检测在N个指令的指令序列中首先出现的分支指令（第k指令）的检测器，用于进行控制的功能逻辑，使得第一到第k指令被执行（N-k + 1）到第N个处理单元。然而，当并行处理是可能的时候，功能逻辑操作使得第一到第N指令由第一到第N个处理单元按顺序执行。另一方面，其中在N个顺序指令中包括分支指令（第k指令），功能逻辑运算，使得第一至第k指令由（N-p + 1） - 通过第N个处理单元。

63. 发明授权

US5507026A Address-translatable graphic processor, data processor and drawing method with employment of the same 失效
标题翻译：地址可翻译的图形处理器，数据处理器和绘图方法与使用相同
公开(公告)号：US5507026A
公开(公告)日：1996-04-09
申请号：US301016
申请日：1994-09-06
申请人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
发明人： Tadashi Fukushima , Shigeru Matsuo , Shoji Yoshida , Tooru Komagawa
IPC分类号： G06F12/10 , G06T1/20 , G06F15/16
CPC分类号： G06T1/20 , G06F12/10
摘要： In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address so as to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit and graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.
摘要翻译：在图形处理系统中，提供了主存储器，包含用于保存显示数据的位图存储器的缓冲器，用于执行涉及从虚拟地址转换为物理地址的数据处理的中央处理单元，以访问主存储器，连接到主存储器和缓冲器的图形处理器，用于将数据处理成显示形式，以及连接到中央处理单元，主存储器和图形处理器的系统总线接口，能够在它们之间交换数据。此外，图形处理系统包括连接到系统总线接口的绘图处理单元，用于将虚拟地址转换为物理地址以访问主存储器并处理该数据;总线仲裁器，用于在需求之间执行仲裁从中央处理单元和图形处理器给出的接口，以及用于断言请求将接口释放到中央处理单元的信号的挂起电路。

64. 发明授权

US5380753A Bath agent 失效
标题翻译：浴剂
公开(公告)号：US5380753A
公开(公告)日：1995-01-10
申请号：US39996
申请日：1993-03-30
申请人： Shoji Yoshida , Kazumi Ogata , Osamu Kawahira
发明人： Shoji Yoshida , Kazumi Ogata , Osamu Kawahira
IPC分类号： A61K8/00 , A61K8/20 , A61K8/23 , A61K8/67 , A61Q19/08 , A61Q19/10 , C07F9/6561 , A61K31/34 , C07D305/12
CPC分类号： A61Q19/10 , A61K8/678 , A61K2800/222
摘要： This invention relates to a bath agent containing sodium chloride and a compound represented by the formula ##STR1## (in the formula R.sub.1 and R.sub.2 are the same or different, and are a hydrogen atom or a methyl group) or its salt.This inventive bath agent is to eliminate and prevent skin itching and to prevent skin aging by preventing and removing effectively the free radical produced on the skin surface by ultraviolet rays.
摘要翻译：本发明涉及含有氯化钠和式（IMA）（式中R1和R2相同或不同，为氢原子或甲基）或其盐的化合物。本发明的浴剂是通过紫外线有效地防止和除去皮肤表面产生的自由基来消除和防止皮肤瘙痒和防止皮肤老化。

65. 发明授权

US5285458A System for suppressing spread of error generated in differential coding 失效
标题翻译：用于抑制差分编码中产生的误差扩散的系统
公开(公告)号：US5285458A
公开(公告)日：1994-02-08
申请号：US672681
申请日：1991-03-20
申请人： Shoji Yoshida
发明人： Shoji Yoshida
IPC分类号： H03M13/00 , H04J3/06 , H04L1/00 , H04L27/18 , G06F11/00
CPC分类号： H04L27/18
摘要： An error suppression system suppresses an error of a data sequence generated in a transmission path between a transmitting terminal and a receiving terminal. The error suppression system includes a data coding circuit in the transmitting terminal for inserting a known bit at a predetermined position of the data sequence and for carrying out a difference logic conversion with respect to the data sequence, a differential coding circuit in the transmitting terminal for carrying out a sum logic conversion with respect to the data sequence which is received from the data coding circuit, a differential decoding circuit in the receiving terminal for carrying out a difference logic conversion with respect to the data sequence received from the differential coding circuit via the transmission path, and a data decoding circuit in the receiving terminal for carrying out a sum logic conversion with respect to the data sequence received from the differential decoding circuit and for restoring the known bit at the predetermined position of the data sequence.
摘要翻译：误差抑制系统抑制在发送终端和接收终端之间的传输路径中产生的数据序列的错误。误差抑制系统包括：发送终端中的数据编码电路，用于在数据序列的预定位置插入已知位，并执行相对于数据序列的差分逻辑转换;发送终端中的差分编码电路，对从数据编码电路接收到的数据序列执行和逻辑转换;接收终端中的差分解码电路，用于对从差分编码电路接收到的数据序列执行差异逻辑转换传输路径和数据解码电路，用于对从差分解码电路接收到的数据序列执行和逻辑转换，并恢复数据序列的预定位置处的已知位。

66. 发明授权

US4252589A Method for forming a mark indication on a tire side wall 失效
标题翻译：在轮胎侧壁上形成标记指示的方法
公开(公告)号：US4252589A
公开(公告)日：1981-02-24
申请号：US953322
申请日：1978-10-20
申请人： Toshio Hayakawa , Shoji Yoshida , Katsuyuki Harakon
发明人： Toshio Hayakawa , Shoji Yoshida , Katsuyuki Harakon
IPC分类号： B29D30/72 , B29B11/00 , B29D30/06 , B60C13/00 , B29H17/02
CPC分类号： B29D30/0633 , B60C13/001 , B29C2037/80 , B29D2030/726 , Y10S152/12
摘要： A mark indication is formed on the tire side wall by sticking partially vulcanized thin rubber sheets provided with mark indications on one side of said sheets along the circumferential direction of the green case at the outer surface corresponding to the side wall of the green case formed on a former and tightly adhering the rubber sheet integrally to the side wall through molding the green case into a toroidal form and vulcanizing said green case.
摘要翻译：在轮胎侧壁上形成有标记指示的部分硫化的薄橡胶片，沿着绿色壳体的圆周方向，在与形成在其上的绿色壳体的侧壁相对应的外表面处，前者，并通过将绿色外壳模制成环形并将所述绿色外壳硫化，将橡胶片一体地紧固到侧壁上。

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