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61. 发明授权

US08355280B2 Data storage system having multi-bit memory device and operating method thereof 有权
标题翻译：具有多位存储装置的数据存储系统及其操作方法
公开(公告)号：US08355280B2
公开(公告)日：2013-01-15
申请号：US13040295
申请日：2011-03-04
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控制器。数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。当存储在缓冲存储器中的数据是与缓冲器程序操作相关的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

62. 发明授权

US08355279B2 Nonvolatile memory device and system, and method of programming a nonvolatile memory device 有权
标题翻译：非易失性存储器件和系统以及非易失性存储器件的编程方法
公开(公告)号：US08355279B2
公开(公告)日：2013-01-15
申请号：US12882378
申请日：2010-09-15
申请人： Sangyong Yoon , Jinman Han , Kitae Park , Joon Young Kwak
发明人： Sangyong Yoon , Jinman Han , Kitae Park , Joon Young Kwak
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5628 , G06F11/1072 , G11C11/10
摘要： A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive number. The controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups, where a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process.
摘要翻译：非易失性存储器包括多个N位多电平单元（MLC）存储器单元和控制器。多个N位MLC存储器单元用于存储N页数据，MLC存储单元中的每一个可编程为2N个阈值电压分布中的任何一个，其中N是正数。控制器被配置为将N页数据编程到MLC存储器单元中，并且执行部分交错处理，其中N页数据被划分为M页组，其中M是正数，并且每个页组包括 N页数据中的至少一个，并且其中M页组中的每一个被应用于纠错码（ECC）电路以产生各个M页组的奇偶校验位，其中误码率（BER）在每个M组内的页面之间通过部分交错处理来均衡。

63. 发明申请

US20120269002A1 PROGRAMMING METHOD FOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：US20120269002A1
公开(公告)日：2012-10-25
申请号：US13443053
申请日：2012-04-10
申请人： Sangyong Yoon , Kitae Park
发明人： Sangyong Yoon , Kitae Park
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying the current logic state of the selected memory transistors. The voltage interval between logic states of the second set of logic states is less than the voltage interval between logic states of the first set of logic states. A target verification voltage for verifying a first memory transistor is at one logic state of the second set is used as a pre-verification voltage for verifying that a second memory transistor to be programmed to higher logic state of the second set.
摘要翻译：一种将非易失性存储器件的存储单元（晶体管）从第一组（先前）逻辑状态编程到第二组（最终）逻辑状态的方法。该方法包括将程序电压施加到选定的存储晶体管; 以及施加预验证电压和目标验证电压以验证所选存储晶体管的当前逻辑状态。第二组逻辑状态的逻辑状态之间的电压间隔小于第一组逻辑状态的逻辑状态之间的电压间隔。用于验证第一存储晶体管的目标验证电压处于第二组的一个逻辑状态，用作预验证电压，用于验证将第二存储晶体管编程为第二组的较高逻辑状态。

64. 发明申请

US20120155168A1 NEGATIVE VOLTAGE GENERATOR, DECODER, NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM USING NEGATIVE VOLTAGE 有权
标题翻译：负电压发生器，解码器，非易失性存储器件和使用负电压的存储器系统
公开(公告)号：US20120155168A1
公开(公告)日：2012-06-21
申请号：US13323868
申请日：2011-12-13
申请人： Moosung Kim , Jaewoo Im , Jae-Duk Yu , Kitae Park , Ohsuk Kwon
发明人： Moosung Kim , Jaewoo Im , Jae-Duk Yu , Kitae Park , Ohsuk Kwon
IPC分类号： G11C16/08 , G11C8/10 , G11C16/34 , G11C16/04 , G05F3/08 , G11C16/26
CPC分类号： G11C11/5628 , G11C5/14 , G11C5/143 , G11C5/145 , G11C5/147 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C16/3459 , G11C2211/5641
摘要： A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock.
摘要翻译：负电压发生器包括被配置为产生直流电压的直流电压发生器，被配置为产生参考电压的参考电压发生器，被配置为产生振荡时钟的振荡器，配置成响应于泵时钟和电压检测器。电压检测器被配置为通过将通过分压直流电压获得的分压与参考电压进行比较来检测负电压，并且基于振荡时钟产生对应于检测到的负电压的泵时钟。

65. 发明授权

US08194455B2 Methods for programming nonvolatile memory devices 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US08194455B2
公开(公告)日：2012-06-05
申请号：US12701037
申请日：2010-02-05
申请人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
发明人： Hyun-Sil Oh , Kitae Park , Soonwook Hwang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： Provided is a method for programming a nonvolatile memory device. The nonvolatile memory device includes a local word line to divide a memory cell string into a first area including a selected word line and a second area not including the selected word line. In the method, word lines of the first area are driven by a first pass voltage and word lines of the second area driven by a second pass voltage higher than the first pass voltage. A cell transistor corresponding to the local word line is turned off after the first pass voltage and the second pass voltage are applied. The selected word line is driven by a program voltage after the cell transistor is turned off.
摘要翻译：提供了一种用于对非易失性存储器件进行编程的方法。非易失性存储器件包括用于将存储单元串划分成包括所选字线的第一区域和不包括所选字线的第二区域的本地字线。在该方法中，第一区域的字线由第一通过电压和由比第一通过电压高的第二通过电压驱动的第二区域的字线驱动。在施加第一通过电压和第二通过电压之后，对应于本地字线的单元晶体管截止。在单元晶体管截止之后，所选字线由编程电压驱动。

66. 发明申请

US20100293393A1 Memory Controller, Memory System Including the Same, and Method for Operating the Same 有权
标题翻译：内存控制器，包括其的内存系统及其操作方法
公开(公告)号：US20100293393A1
公开(公告)日：2010-11-18
申请号：US12777676
申请日：2010-05-11
申请人： Kitae Park
发明人： Kitae Park
IPC分类号： G06F12/14
CPC分类号： G06F12/0246 , G06F2212/1032
摘要： A memory controller includes a first interface unit, a processor, a randomization unit, a state conversion unit, and a second interface unit. The first interface unit exchanges data with an external device, and the processor determines whether to randomize or state-convert the received data. The randomization unit randomizes data received through the first interface unit in response to the processor and generates randomization information in response to the randomization operation. The state conversion unit state-converts data received through the first interface unit in response to the processor and generates conversion information in response to the state conversion operation. The second interface unit receives the randomized data and the randomization information from the randomization unit, receives the state-converted data and the conversion information from the state conversion unit, and exchanges at least one of the randomized data, the randomization information, the state-converted data and the conversion information with a memory.
摘要翻译：存储器控制器包括第一接口单元，处理器，随机化单元，状态转换单元和第二接口单元。第一接口单元与外部设备交换数据，并且处理器确定是否对所接收的数据进行随机化或状态转换。随机化单元响应于处理器随机化通过第一接口单元接收的数据，并且响应于随机化操作生成随机化信息。状态转换单元响应于处理器对通过第一接口单元接收的数据进行状态转换，并响应于状态转换操作产生转换信息。第二接口单元从随机化单元接收随机数据和随机化信息，从状态转换单元接收状态转换数据和转换信息，并且交换随机数据，随机化信息，状态转换信息中的至少一个，转换数据和转换信息。

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