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61. 发明授权

US5882970A Method for fabricating flash memory cell having a decreased overlapped region between its source and gate 失效
标题翻译：一种用于制造其源极和栅极之间具有减小的重叠区域的闪存单元的方法
公开(公告)号：US5882970A
公开(公告)日：1999-03-16
申请号：US552428
申请日：1995-11-03
申请人： Chih-Hung Lin , Hwi-Huang Chen , Gary Hong , Chen-Chiu Hsue
发明人： Chih-Hung Lin , Hwi-Huang Chen , Gary Hong , Chen-Chiu Hsue
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.
摘要翻译：闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域，从而增加源极区域和衬底之间的击穿电压。

62. 发明授权

US5852313A Flash memory cell structure having a high gate-coupling coefficient and a select gate 失效
标题翻译：具有高栅极耦合系数和选择栅极的闪存单元结构
公开(公告)号：US5852313A
公开(公告)日：1998-12-22
申请号：US967940
申请日：1997-11-12
申请人： Gary Hong , Patrick Wang , Wenchi Ting
发明人： Gary Hong , Patrick Wang , Wenchi Ting
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/115
摘要： A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.
摘要翻译：一种闪速存储单元结构，包括具有形成在其上的第一晶体管和第二晶体管的半导体衬底。第一晶体管具有堆叠栅极和第一源极/漏极区域，其中堆叠栅极还包括浮置栅极和控制栅极。控制栅极形成在浮动栅极上方。第二晶体管与第一晶体管串联电连接。第二晶体管用作选择晶体管，并且包括栅极和第二源极/漏极区域。

63. 发明授权

US5849625A Planar field oxide isolation process for semiconductor integrated circuit devices using liquid phase deposition 失效
标题翻译：使用液相沉积的半导体集成电路器件的平面场氧化物隔离工艺
公开(公告)号：US5849625A
公开(公告)日：1998-12-15
申请号：US807885
申请日：1997-02-26
申请人： Chen-Chiu Hsue , Gary Hong
发明人： Chen-Chiu Hsue , Gary Hong
IPC分类号： H01L21/762 , H01L2/76
CPC分类号： H01L21/76205 , H01L21/76237
摘要： A process for fabricating an improved planar field oxide (FOX) structure on a silicon substrate was achieved. The process involves forming recessed areas in the silicon substrate where the field oxide is require. A thin silicon oxide is formed on the surface of the recessed areas as a nucleation layer and then a thicker silicon oxide layer is selectively deposited in the recess areas by Liquid Phase Deposition (LPD). The planar FOX structure formed by LPD can be used in conjunction with a FOX structure formed by the conventional LOCal Oxidation of Silicon (LOCOS) process on the same substrate. The planar field oxide formed by LPD eliminates the bird beak structure and the lateral diffusion of the channel stop implant commonly associated with the LOCOS structure.
摘要翻译：实现了在硅衬底上制造改进的平面场氧化物（FOX）结构的工艺。该方法包括在需要场氧化物的硅衬底中形成凹陷区域。在凹陷区域的表面上形成薄的氧化硅作为成核层，然后通过液相沉积（LPD）在凹陷区域中选择性地沉积更厚的氧化硅层。由LPD形成的平面FOX结构可以与在同一衬底上通过常规的局部氧化硅（LOCOS）工艺形成的FOX结构结合使用。由LPD形成的平面场氧化物消除了鸟喙结构和通常与LOCOS结构相关联的通道停止植入物的横向扩散。

64. 发明授权

US5700708A Process for fabricating storage capacitor for DRAM memory cell 失效
标题翻译：制造用于DRAM存储单元的存储电容器的工艺
公开(公告)号：US5700708A
公开(公告)日：1997-12-23
申请号：US665386
申请日：1996-06-18
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.
摘要翻译：一种用于制造DRAM存储器件的存储单元单元的存储电容器以实现增加的电容值的过程。该工艺包括首先在器件的硅衬底上形成包括栅极，源极区和漏极区的晶体管。栅极包括被绝缘层覆盖的第一多晶硅层。形成覆盖晶体管的氮化硅层，并且在氮化硅层上形成氧化硅层。在氧化硅层和暴露晶体管漏极/源极区域的表面的氮化硅层上形成接触开口。氧化硅层具有比其延伸的氮化硅层的边缘朝向接触开口的空腔延伸的边缘部分。然后在接触开口中形成第二多晶硅层，覆盖暴露的漏极区域，栅极以及氧化硅层和氮化硅层的边缘部分。因此，第二多晶硅层提供存储电容器的第一电极。在第二多晶硅层上形成电介质层以提供存储电容器的电介质，并且在电介质层上形成第三多晶硅层以提供存储电容器的第二电极。

65. 发明授权

US5675162A EPROM, flash memory with high coupling ratio 失效
标题翻译： EPROM，具有高耦合比的闪存
公开(公告)号：US5675162A
公开(公告)日：1997-10-07
申请号：US641411
申请日：1996-04-30
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the substrate, a first floating gate layer formed on the dielectric layer, a second floating gate layer formed on the the first floating gate layer, a second dielectric material deposited upon the surface of the first floating gate electrode, a control gate electrode deposited upon the surface of the additional dielectric material, and means for applying a voltage to the control gate electrode.
摘要翻译：半导体器件形成在其表面上的衬底中轻掺杂有掺杂剂，源区和漏区的衬底上，沉积在衬底上的电介质层，形成在电介质层上的第一浮栅，第二浮栅形成在第一浮栅上的浮置栅层，沉积在第一浮栅电极的表面上的第二电介质材料，沉积在附加电介质材料的表面上的控制栅极电极，以及向控制电极施加电压的装置栅电极。

66. 发明授权

US5646436A Read only memory (ROM) device produced by self-aligned implantation 失效
标题翻译：通过自对准植入产生的只读存储器（ROM）器件
公开(公告)号：US5646436A
公开(公告)日：1997-07-08
申请号：US536934
申请日：1995-09-29
申请人： Gary Hong , Chen-Chiu Hsue , Chen-Hui Chung
发明人： Gary Hong , Chen-Chiu Hsue , Chen-Hui Chung
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/265
CPC分类号： H01L27/1126 , H01L27/112
摘要： A Read-Only Memory (ROM) device produced by self-aligned implantation. First, a non-coded mask ROM with a silicon substrate, a plurality of bit-lines formed in the substrate, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together form arrays of memory cells, is provided. Next, an aligning layer is formed above the word-lines. A photoresist is thereafter coated on the surface of the aligning layer. Then, portions of the photoresist not covered by a mask pattern are etched away to the aligning layer so as to provide openings exposing portions of the memory cells that will be programmed to operate in a first conduction state. Portions of the aligning layer exposed through the openings are then removed, after which impurities are implanted through the openings and into the substrate to enable the memory cells that are to operate in the first conduction state, and leave other non-programmed memory cells operating in a second conduction state.
摘要翻译：通过自对准植入制造的只读存储器（ROM）器件。首先，具有硅衬底的非编码掩模ROM，在衬底中形成的多个位线，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，其一起提供了存储单元的阵列。接下来，在字线上形成对准层。然后将光致抗蚀剂涂覆在对准层的表面上。然后，未被掩模图案覆盖的部分光致抗蚀剂被蚀刻掉到对准层上，以便提供露出将被编程为在第一导通状态下操作的存储单元部分的开口。然后去除通过开口暴露的对准层的部分，之后通过开口注入杂质并进入衬底，以使得能够在第一导通状态下操作的存储器单元，并且使其他非编程存储器单元在第二导通状态。

67. 发明授权

US5635749A High performance field effect transistor with lai region 失效
标题翻译：高性能场效应晶体管
公开(公告)号：US5635749A
公开(公告)日：1997-06-03
申请号：US537138
申请日：1995-09-29
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/1045
摘要： A MOSFET transistor device with a gate formed over a lightly doped semiconductor substrate with a gate, and a source region and a drain region. V.sub.T1 ions are uniformly implanted into the surface of the substrate forming a V.sub.T region with substantially uniform doping in the upper portion of the substrate near the surface thereof. A gate oxide layer is formed on the substrate. A gate conductor is deposited over the gate oxide layer. A large angle implant is implanted into the region of the device over the source region. Then ions are implanted to form the source and drain regions which are self-aligned with the gate.
摘要翻译： MOSFET晶体管器件，其栅极形成在具有栅极的轻掺杂半导体衬底上，以及源极区和漏极区。将VT1离子均匀地注入基片的表面，形成具有基本均匀掺杂的VT区域，该VT区域在其表面附近的衬底上部。在衬底上形成栅氧化层。栅极导体沉积在栅极氧化物层上。在源区域上的器件区域中注入大角度植入物。然后注入离子以形成与栅极自对准的源区和漏区。

68. 发明授权

US5596230A Interconnection with self-aligned via plug 失效
标题翻译：通过插头自对准互连
公开(公告)号：US5596230A
公开(公告)日：1997-01-21
申请号：US583197
申请日：1996-01-04
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/768 , H01L23/522 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76801 , H01L21/76897 , H01L23/5226 , H01L2924/0002
摘要： A device and a method of formation on a substrate of a semiconductor interconnection via structure for semiconductor devices is provided. Initially, form a first metal layer on the substrate, a first dielectric layer upon the first metal layer, and a mask upon the dielectric layer with a metal etching pattern therein. Then, etch through the first dielectric layer and the first metal layer to the substrate forming trenches between metal lines formed from the first metal layer covered with the dielectric layer. Next, form a first etch stop layer upon the surface of the the first dielectric layer and planarize it, a second dielectric layer above the etch stop layer, and a second etch stop layer on the second dielectric layer. Then, pattern the second dielectric and the second etch stop layer and etch to form a via hole down to a surface of the first metal layer. Then, form a second metal layer and a metal plug in the via hole extending into contact with the first metal layer.
摘要翻译：提供了一种用于半导体器件的半导体互连通孔结构的衬底上的器件和方法。首先，在基板上形成第一金属层，在第一金属层上形成第一介电层，在介质层上形成具有金属蚀刻图案的掩模。然后，通过第一介电层和第一金属层蚀刻到由覆盖有电介质层的第一金属层形成的金属线之间形成沟槽的衬底。接下来，在第一介电层的表面上形成第一蚀刻停止层并使其平坦化，在蚀刻停止层上方的第二介电层和第二介电层上的第二蚀刻停止层。然后，对第二电介质和第二蚀刻停止层进行图案化并蚀刻以形成到第一金属层的表面的通孔。然后，在通孔中形成与第一金属层接触的第二金属层和金属塞。

69. 发明授权

US5576228A Method for fabricating polycide gate MOSFET devices 失效
公开(公告)号：US5576228A
公开(公告)日：1996-11-19
申请号：US446225
申请日：1995-05-22
申请人： Ancheor Chen , Gary Hong
发明人： Ancheor Chen , Gary Hong
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28061 , H01L29/6656
摘要： A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.

70. 发明授权

US5556798A Method for isolating non-volatile memory cells 失效
标题翻译：隔离非易失性存储单元的方法
公开(公告)号：US5556798A
公开(公告)日：1996-09-17
申请号：US347715
申请日：1994-12-01
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/762 , H01L21/8247 , A01L21/8247
CPC分类号： H01L27/11521 , H01L21/762
摘要： A method of fabricating semiconductor integrated circuit non-volatile memory devices having memory cell isolation between the memory cells without increasing device dimension. Active regions are defined by forming field oxide layers on a on semiconductor substrate of a first type. Lightly-doped regions of the first type are formed underneath field oxide layers. Additional heavily-doped regions of the first type are formed within each of the lightly-doped regions. Active regions on the semiconductor substrate are implanted with impurities of a second type to form drains and sources for the memory cells. Floating gate layers are formed on tunnel oxide layers, the tunnel oxide layers separating the floating gate layers from the active regions. The presence of the lightly-doped region improves the breakdown voltage, while the additional heavily-doped regions within each of the lightly-doped regions increases threshold and punchthrough voltages for the inherent parasitic transistors of the memory device.
摘要翻译：一种在不增加器件尺寸的情况下制造在存储器单元之间具有存储单元隔离的半导体集成电路非易失性存储器件的方法。通过在第一类型的半导体衬底上形成场氧化物层来限定有源区。第一类型的轻掺杂区域形成在场氧化物层下面。在每个轻掺杂区域内形成第一类型的附加重掺杂区域。在半导体衬底上的有源区域注入第二类型的杂质以形成存储器单元的漏极和源极。浮动栅极层形成在隧道氧化物层上，隧道氧化物层将浮动栅极层与活性区域分开。轻掺杂区域的存在改善了击穿电压，而每个轻掺杂区域内的附加重掺杂区域增加了存储器件固有寄生晶体管的阈值和穿透电压。

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