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61. 发明申请

US20100165300A1 ILLUMINATION APPARATUS AND PROJECTION DISPLAY APPARATUS USING THE SAME 失效
标题翻译：照明装置和投影显示装置
公开(公告)号：US20100165300A1
公开(公告)日：2010-07-01
申请号：US12161109
申请日：2007-01-18
申请人： Yusaku Shimaoka , Atsushi Hatakeyama , Yoshimasa Fushimi , Hiroshi Miyai
发明人： Yusaku Shimaoka , Atsushi Hatakeyama , Yoshimasa Fushimi , Hiroshi Miyai
IPC分类号： G03B21/14 , F21S2/00 , F21V5/00 , G02B6/00
CPC分类号： G03B21/208 , G03B33/06
摘要： An illumination apparatus includes a light source (1), a first integrator (11) into which light from the light source (1) enters, and a second integrator (33) into which light exiting from the first integrator (11) enters. Accordingly, the aperture shape of the first integrator (11) can be optimally designed, so that the light utilization efficiency can be increased. Furthermore, even when the length of the first integrator (11) is reduced, a deficiency in the light uniformity due to the first integrator (11) is compensated for by the second integrator (33), so that high uniformity can be secured at the surface to be illuminated.
摘要翻译：照明装置包括光源（1），来自光源（1）的光入射的第一积分器（11）和从第一积分器（11）射出的光进入的第二积分器（33）。因此，可以最佳地设计第一积分器（11）的开口形状，从而可以提高光利用效率。此外，即使当第一积分器（11）的长度减小时，由第一积分器（11）导致的光均匀性的不足由第二积分器（33）补偿，从而可以确保高的均匀性要照亮的表面。

62. 发明授权

US07184296B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US07184296B2
公开(公告)日：2007-02-27
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C11/00
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

63. 发明申请

US20060218279A1 Method for controlling a management computer 有权
标题翻译：管理计算机的控制方法
公开(公告)号：US20060218279A1
公开(公告)日：2006-09-28
申请号：US11312394
申请日：2005-12-21
申请人： Akihiko Yamaguchi , Atsushi Hatakeyama
发明人： Akihiko Yamaguchi , Atsushi Hatakeyama
IPC分类号： G06F15/173
CPC分类号： H04L67/1008 , H04L67/02 , H04L67/1002
摘要： A method for controlling a management computer connected to a server for permitting communications therebetween, wherein the server transmits to a client the result of processing executed in response to each processing request sent from the client. The management computer stores an allowance for a value indicative of a load on the server, receives from the server a value calculated on the basis of the number of processing requests from the client and the value indicative of the load on the server. The management computer calculates an allowance for the value calculated from the number of processing requests, based on the value calculated from the number of processing requests, the allowance for the value indicative of the load, and the value indicative of the load, and transmits to the server the calculated allowance for the value calculated from the number of processing requests.
摘要翻译：一种用于控制连接到服务器的管理计算机的方法，用于允许其间的通信，其中服务器响应于从客户端发送的每个处理请求向客户端发送处理结果。管理计算机存储指示服务器上的负载的值的容许量，从服务器接收根据来自客户端的处理请求数计算的值和表示服务器上的负载的值。管理计算机根据从处理请求的数量，表示负载的值的允许值和表示负载的值计算出的值，根据处理请求的数量计算出的值的容许量，并发送到服务器根据处理请求的数量计算出的值的计算余量。

64. 发明授权

US06774655B2 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06774655B2
公开(公告)日：2004-08-10
申请号：US10622472
申请日：2003-07-21
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

65. 发明授权

US06626378B2 Shower apparatus 失效
公开(公告)号：US06626378B2
公开(公告)日：2003-09-30
申请号：US10126092
申请日：2002-04-18
申请人： Tsutomu Sasaki , Satoshi Sasaki , Atsushi Hatakeyama
发明人： Tsutomu Sasaki , Satoshi Sasaki , Atsushi Hatakeyama
IPC分类号： A62C502
CPC分类号： A47K3/40 , A47K3/283 , C02F1/42 , E03C1/0408 , E03C2201/40
摘要： A hollow bar is provided in a bathroom and connected with a faucet 10 and a shower head 1. The hollow bar comprises a slide bar 3 for the hook 2 of the shower head or a grip bar 15 for a user. Water treating material such as a filter medium, ion exchange resin and ceramics is placed in the hollow bar and water jetted from the faucet 10 passes the water treating material in the hollow bar. The water is treated by the water treating material and the treated water is guided to and dispensed from the shower head.

66. 发明授权

US06621283B1 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06621283B1
公开(公告)日：2003-09-16
申请号：US09437221
申请日：1999-11-10
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

67. 发明授权

US06422484B1 Shower apparatus 失效
标题翻译：淋浴设备
公开(公告)号：US06422484B1
公开(公告)日：2002-07-23
申请号：US09634792
申请日：2000-08-09
申请人： Tsutomu Sasaki , Satoshi Sasaki , Atsushi Hatakeyama
发明人： Tsutomu Sasaki , Satoshi Sasaki , Atsushi Hatakeyama
IPC分类号： A62C502
CPC分类号： A47K3/40 , A47K3/283 , C02F1/42 , E03C1/0408 , E03C2201/40
摘要： A hollow bar is provided in a bathroom and connected with a faucet 10 and a showerhead 1. The hollow bar comprises a slide bar 3 for the hook 2 of the showerhead or a grip bar 15 for a user. Water treating material such as a filter medium, ion exchange resin and ceramics is placed in the hollow bar and water jetted from the faucet 10 passes the water treating material in the hollow bar. The water is treated by the water treating material and the treated water is guided to and dispensed from the showerhead.
摘要翻译：中空杆设置在浴室中并与龙头10和喷头1连接。中空杆包括用于喷头的钩2的滑杆3或用于使用者的把手15。将水处理材料如过滤介质，离子交换树脂和陶瓷放置在空心棒中，并且从龙头10喷射的水通过中空棒中的水处理材料。水由水处理材料处理，处理后的水被引导并从喷头中分配。

68. 发明授权

US06236605B1 Semiconductor integrated circuit and semiconductor memory device including overdriving sense amplifier 有权
标题翻译：半导体集成电路和包括过驱动读出放大器的半导体存储器件
公开(公告)号：US06236605B1
公开(公告)日：2001-05-22
申请号：US09501269
申请日：2000-02-09
申请人： Kaoru Mori , Ayako Kitamoto , Masato Matsumiya , Masato Takita , Shinichi Yamada , Koichi Nishimura , Atsushi Hatakeyama
发明人： Kaoru Mori , Ayako Kitamoto , Masato Matsumiya , Masato Takita , Shinichi Yamada , Koichi Nishimura , Atsushi Hatakeyama
IPC分类号： G11C700
CPC分类号： G11C7/08 , G11C5/025 , G11C5/14 , G11C7/065 , G11C11/4074 , G11C11/4091 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2207/065
摘要： A transistor of a driver in the semiconductor integrated circuit according to the present invention has its gate connected to a controlling circuit, and has its drain connected to a sense amplifier. The controlling circuit supplies the gate of the transistor with a gate-to-source voltage exceeding or below other power supply voltages. The drain-to-source resistance of the transistor in the on state becomes sufficiently lower as compared with that in the case of supplying the power supply voltages between the gate and source of the transistor. Accordingly, the amplifying speed of the sense amplifier is heightened without altering the sense amplifier and the driver. Besides, the amplifying speed of the sense amplifier is heightened without raising the power supply voltage which supplies the carriers to the driver. The semiconductor memory device according to the present invention switches the driving supply voltage for the sense amplifier from the first supply voltage, to the second supply voltage lower than the first voltage. The timing at which the first supply voltage is switched to the second supply voltage is controlled in accordance with the voltage on a dummy bit line which is driven by a monitoring sense amplifier. Accordingly, even when the driving speed of the sense amplifier using the overdriving system has fluctuated due to the fluctuation of the first supply voltage, the driving supply voltage of the sense amplifier can be always switched to the second supply voltage at the appropriate timing.
摘要翻译：根据本发明的半导体集成电路中的驱动器的晶体管的栅极连接到控制电路，并且其漏极连接到读出放大器。控制电路为晶体管的栅极提供超过或低于其他电源电压的栅极至源极电压。与在晶体管的栅极和源极之间提供电源电压的情况相比，导通状态下的晶体管的漏极 - 源极电阻变得足够低。因此，增强了读出放大器的放大速度，而不改变读出放大器和驱动器。此外，增强读出放大器的放大速度，而不会提高向驱动器提供载波的电源电压。根据本发明的半导体存储器件将读出放大器的驱动电源电压从第一电源电压切换到低于第一电压的第二电源电压。根据由监视读出放大器驱动的虚拟位线上的电压来控制第一电源电压切换到第二电源电压的定时。因此，即使当使用过驱动系统的读出放大器的驱动速度由于第一电源电压的波动而波动时，也可以在适当的定时将读出放大器的驱动电源电压始终切换到第二电源电压。

69. 发明授权

US5874853A Semiconductor integrated circuit system 失效
标题翻译：半导体集成电路系统
公开(公告)号：US5874853A
公开(公告)日：1999-02-23
申请号：US863356
申请日：1997-05-27
申请人： Shusaku Yamaguchi , Atsushi Hatakeyama , Masato Takita , Tadao Aikawa , Hirohiko Mochizuki
发明人： Shusaku Yamaguchi , Atsushi Hatakeyama , Masato Takita , Tadao Aikawa , Hirohiko Mochizuki
IPC分类号： G11C11/413 , G11C11/407 , G11C11/409 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , Y10T307/724
摘要： A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.
摘要翻译：半导体集成电路系统包括提供第一源电源电压的第一电源线和提供第二源电源电压的第二电源线。当检测到第一源电源电压的上升沿时，第一边缘检测单元输出第一边沿检测信号。当检测到第二源电源电压的上升沿时，第二边缘检测单元输出第二边缘检测信号。输出单元连接到第一电力线，并且在数据输出周期中向数据终端输出数据，并且响应于第一边缘检测信号将数据端子设置为高阻抗状态。输出控制单元连接到第二电力线，并且根据数据输出周期中的读取数据信号来控制输出单元，并且响应于第二边缘检测信号来控制输出单元，使得数据终端通过输出单元设置在高阻抗状态。

70. 发明授权

US5862094A Semiconductor device and a semiconductor memory device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US5862094A
公开(公告)日：1999-01-19
申请号：US870547
申请日：1997-06-06
申请人： Kuninori Kawabata , Atsushi Hatakeyama
发明人： Kuninori Kawabata , Atsushi Hatakeyama
IPC分类号： G11C11/401 , G11C11/403 , G11C11/406 , G11C29/14 , G11C13/00
CPC分类号： G11C11/406 , G11C29/14
摘要： According to the present invention, a semiconductor memory device includes an oscillator for generating with a predetermined cycle a timing signal for performing a refresh operation for the memory cell array. The oscillator includes an oscillation circuit, for receiving a predetermined characteristic value and generating the timing signal having the cycle in accordance with the characteristic value; a characteristic value generation circuit, having a programmable memory for generating an adjustment signal for an adjustment of the characteristic value, for transmitting to the oscillation circuit the characteristic value adjusted in accordance with the adjustment signal; and a confirmation switch for generating, instead of the memory, the adjustment signal for a test in accordance with a test entry signal.
摘要翻译：根据本发明，半导体存储器件包括用于以预定周期产生用于对存储单元阵列进行刷新操作的定时信号的振荡器。所述振荡器包括：振荡电路，用于接收预定的特征值，并产生具有根据该特征值的周期的定时信号; 特征值生成电路，具有可编程存储器，用于产生用于调整特征值的调整信号，向振荡电路发送根据调整信号调整的特性值; 以及确认开关，用于根据测试输入信号产生用于测试的调整信号的存储器而不是存储器。

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