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61. 发明申请

US20190253362A1 Ability to Detect Unlimited Elephant Flows 审中-公开
公开(公告)号：US20190253362A1
公开(公告)日：2019-08-15
申请号：US15896128
申请日：2018-02-14
申请人： Mellanox Technologies, Ltd.
发明人： Jacob Ruthstein , David Mozes , Dror Bohrer , Ariel Shahar , Lior Narkis , Noam Bloch
IPC分类号： H04L12/851 , H04L12/801 , H04L12/26
摘要： Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

62. 发明授权

US10305772B2 Using a single work item to send multiple messages 有权
公开(公告)号：US10305772B2
公开(公告)日：2019-05-28
申请号：US15077945
申请日：2016-03-23
申请人： Mellanox Technologies Ltd.
发明人： Itay Zur , Noam Bloch , Ariel Shahar , Dotan Finkelstein
IPC分类号： H04L12/26 , H04L12/861 , H04L29/08
摘要： A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.

63. 发明申请

US20180004705A1 Selective acknowledgment of RDMA packets 审中-公开
公开(公告)号：US20180004705A1
公开(公告)日：2018-01-04
申请号：US15196088
申请日：2016-06-29
申请人： Mellanox Technologies Ltd.
发明人： Adi Menachem , Ariel Shahar , Noam Bloch , Diego Crupnicoff , Michael Kagan
IPC分类号： G06F15/173 , H04L29/06 , H04L5/00
CPC分类号： G06F15/17331 , G06F13/28 , H04L1/1614 , H04L1/1635 , H04L1/1809 , H04L69/16
摘要： A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.

64. 发明申请

US20170068640A1 NETWORK MEMORY 有权
标题翻译：网络存储器
公开(公告)号：US20170068640A1
公开(公告)日：2017-03-09
申请号：US14847021
申请日：2015-09-08
申请人： MELLANOX TECHNOLOGIES LTD.
发明人： Ariel Shahar , Maria Lubeznov
IPC分类号： G06F15/173 , H04L12/861 , H04L29/08
CPC分类号： G06F15/17331 , H04L49/15 , H04L49/9068 , H04L67/1097
摘要： Communication apparatus includes a host interface for connection, via a host bus, to a host processor and a host memory, which is mapped to an address space of the host bus, and a network interface, configured to transmit and receive packets over a network. A local memory is configured to hold data in a memory space that is not mapped to the address space of the host bus. Packet processing circuitry, which is connected between the host interface and the network interface and is connected to the local memory, is configured to receive from the network interface a packet carrying a remote direct memory access (RDMA) request that is directed to an address in the local memory, and to service the RDMA request by accessing the data in the local memory.
摘要翻译：通信装置包括主机接口，用于经由主机总线连接到被映射到主机总线的地址空间的主机处理器和主机存储器，以及被配置为经由网络发送和接收分组的网络接口。本地存储器被配置为将数据保存在未映射到主机总线的地址空间的存储器空间中。连接在主机接口和网络接口之间并连接到本地存储器的分组处理电路被配置为从网络接口接收携带指向地址的远程直接存储器访问（RDMA）请求的分组本地内存，并通过访问本地内存中的数据来服务RDMA请求。

65. 发明公开

US20240193106A1 Cross Address-Space Bridging 审中-公开
公开(公告)号：US20240193106A1
公开(公告)日：2024-06-13
申请号：US18444804
申请日：2024-02-19
申请人： Mellanox Technologies, Ltd.
发明人： Idan Burstein , Dotan David Levi , Ariel Shahar , Lior Narkis , Igor Voks , Noam Bloch , Shay Aisman
IPC分类号： G06F13/16 , G06F9/455 , G06F9/46 , G06F12/1045 , G06F13/38 , G06F13/42 , G06F15/173
CPC分类号： G06F13/1668 , G06F9/45558 , G06F9/466 , G06F12/1054 , G06F12/1063 , G06F13/387 , G06F13/4221 , G06F15/17331 , G06F2009/45579
摘要： A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

66. 发明授权

US11966355B2 Network adapter with a common queue for both networking and data manipulation work requests 有权
公开(公告)号：US11966355B2
公开(公告)日：2024-04-23
申请号：US16224834
申请日：2018-12-19
申请人： Mellanox Technologies, Ltd.
发明人： Ariel Shahar , Roee Moyal , Ali Ayoub , Michael Kagan
IPC分类号： G06F15/173 , G06F13/28 , G06F15/167 , H04L9/06 , H04L9/32
CPC分类号： G06F15/17331 , G06F13/28 , G06F15/167 , G06F15/1735 , H04L9/0631 , H04L9/0643 , H04L9/3247
摘要： A network adapter includes a network interface that communicates packets over a network, a host interface connected locally to a host processor and to a host memory, and processing circuitry, coupled between the network interface and the host interface, and is configured to receive in a common queue, via the host interface, (i) a processing work item specifying a source buffer in the host memory, a data processing operation, and a first address in the host memory, and (ii) an RDMA write work item specifying the first address, and a second address in a remote memory. In response to the processing work item, the processing circuitry reads data from the source buffer, applies the data processing operation, and stores the processed data in the first address. In response to the RDMA write work item the processing circuitry transmits the processed data, over the network, for storage in the second address.

67. 发明授权

US11940933B2 Cross address-space bridging 有权
公开(公告)号：US11940933B2
公开(公告)日：2024-03-26
申请号：US17189303
申请日：2021-03-02
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Idan Burstein , Dotan David Levi , Ariel Shahar , Lior Narkis , Igor Voks , Noam Bloch , Shay Aisman
IPC分类号： G06F13/16 , G06F9/455 , G06F9/46 , G06F12/1045 , G06F13/38 , G06F13/42 , G06F15/173
CPC分类号： G06F13/1668 , G06F9/45558 , G06F9/466 , G06F12/1054 , G06F12/1063 , G06F13/387 , G06F13/4221 , G06F15/17331 , G06F2009/45579
摘要： A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

68. 发明授权

US11847487B2 Task completion system allowing tasks to be completed out of order while reporting completion in the original ordering my 有权
公开(公告)号：US11847487B2
公开(公告)日：2023-12-19
申请号：US17331657
申请日：2021-05-27
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Ariel Shahar , Roee Moyal
IPC分类号： G06F9/46 , G06F9/48 , G06F9/54
CPC分类号： G06F9/4843 , G06F9/546 , G06F2209/548
摘要： A method using a memory and queue handling logic, including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C.

69. 发明公开

US20230214341A1 Multi-socket network interface controller with consistent transaction ordering 审中-公开
公开(公告)号：US20230214341A1
公开(公告)日：2023-07-06
申请号：US18174668
申请日：2023-02-27
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
IPC分类号： G06F13/28 , G06F3/06
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0655 , G06F3/0673 , G06F2213/28
摘要： Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

70. 发明授权

US11558175B2 Cryptographic data communication apparatus 有权
公开(公告)号：US11558175B2
公开(公告)日：2023-01-17
申请号：US17233591
申请日：2021-04-19
申请人： MELLANOX TECHNOLOGIES, LTD.
发明人： Miriam Menes , Noam Bloch , Adi Menachem , Idan Burstein , Ariel Shahar , Maxim Fudim
IPC分类号： H04L9/06 , H04L9/08 , H04L9/32
摘要： In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.

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